EP9315 Datasheet, PDF (10/64 Pages) Cirrus Logic – Enhanced Universal Platform System-on-Chip Processor

EP9315
Enhanced Universal Platform SOC Processor
Real-Time Clock with Software Trim
The software trim feature on the real time clock (RTC)
provides software controlled digital compensation of the
32.768 kHz input clock. This compensation is accurate to
± 1.24 sec/month.
Note: A real time clock must be connected to RTCXTALI or
the EP9315 device will not boot.
Table L. Real-Time Clock with Pin Assignments
Pin Mnemonic
RTCXTALI
RTCXTALO
Pin Name - Description
Real-Time Clock Oscillator Input
Real-Time Clock Oscillator Output
PLL and Clocking
The processor and the peripheral clocks operate from a
single 14.7456 MHz crystal.
The real time clock operates from a 32.768 kHz external
oscillator.
Table M. PLL and Clocking Pin Assignments
Pin Mnemonic
Pin Name - Description
XTALI
XTALO
VDD_PLL
GND_PLL
Main Oscillator Input
Main Oscillator Output
Main Oscillator Power
Main Oscillator Ground
Timers
The Watchdog Timer insures proper operation by
requiring periodic attention to prevent a reset-on-time-
out.
Two 16-bit timers operate as free running down-counters
or as periodic timers for fixed interval interrupts and have
a range of 0.03 ms to 4.27 seconds.
One 32-bit timer, plus a 6-bit prescale counter, has a
range of 0.03 µs to 73.3 hours.
One 40-bit debug timer, plus 6-bit prescale counter, has a
range of 1.0 µs to 12.7 days.
Interrupt Controller
The interrupt controller allows up to 64 interrupts to
generate an Interrupt Request (IRQ) or Fast Interrupt
Request (FIQ) signal to the processor core. Thirty-two
hardware priority assignments are provided for assisting
IRQ vectoring, and two levels are provided for FIQ
vectoring. This allows time critical interrupts to be
processed in the shortest time possible. Internal
interrupts may be programmed as active-high or active-
low, level-sensitive inputs. GPIO may be programmed as
active-high level-sensitive, active-low level-sensitive,
rising-edge-triggered, falling-edge-triggered, or combined
rising/falling-edge-triggered.
• Supports 64 interrupts from a variety of sources (such
as UARTs, GPIO, and key matrix)
• Routes interrupt sources to either the ARM920T’s
IRQ or FIQ (Fast IRQ) inputs
• Four dedicated off-chip interrupt lines INT[3:0]
operate as active-high, level-sensitive interrupts
• Any of the 16 GPIO lines maybe configured to
generate interrupts
• Software supported priority mask for all FIQs and
IRQs
Table N. External Interrupt Pin Assignment
Pin Mnemonic
Pin Name - Description
INT[3:0]
External Interrupt 3-0
Dual LED Drivers
Two pins are assigned specifically to drive external
LEDs.
Table O. Dual LED Pin Assignments
Pin Mnemonic
Pin Name -
Description
Alternative Usage
GRLED
REDLED
Green LED
Red LED
General Purpose I/O
General Purpose I/O
General Purpose Input/Output (GPIO)
The 16 EGPIO pins may each be configured individually
as an output, an input, or an interrupt input. Port F may
be configured as GPIO. Each Port F pin may be
configured individually as an output, input or an interrupt
input.
There are 23 pins that may be used as alternate inputs or
outputs, but do not support interrupts. These pins are:
• Key Matrix ROW[7:0], COL[7:0]
• Ethernet MDIO
• Both LED Outputs
• Two-wire Clock and Data
• SLA [1:0]
6 pins may alternatively be used as inputs only:
• CTSn, DSRn / DCDn
• 4 Interrupt Lines
2 pins may alternatively be used as outputs only:
• RTSn
• ARSTn
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