EP9315 Datasheet, PDF (26/64 Pages) Cirrus Logic – Enhanced Universal Platform System-on-Chip Processor

EP9315
Enhanced Universal Platform SOC Processor
Static Memory Burst Write Cycle
Parameter
AD setup to WRn assert time
AD hold from WRn deassert time
WRN/DQMn deassert to AD transition time
CSn hold from WRn deassert time
CSn to WRn assert delay time
CSn to DQMn assert delay time
DQMn assert time
DQMn deassert time
WRn assert time
WRn deassert time
WRn/DQMn deassert to DA transition time
WRn/DQMn assert to DA valid time
Symbol
t_ADs
t_ADh
t_ADd
t_CSh
t_WRd
t_DQMd
t_DQpwL
t_DQpwH
t_WRpwL
t_WRpwH
t_DAh
t_DAv
Min
t_HCLK − 3
t_HCLK × 2
7
t_HCLK
Typ
t_HCLK × (WST1 + 1)
t_HCLK × (WST1 + 11)
Max
t_HCLK + 6
2
1
(t_HCLK × 2) + 14
(t_HCLK × 2) + 7
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
t_ADs
t_ADd
AD
CSn
WRn
t_WRd
RD
DQMn
t_DQMd
DA
t_WRpwL
t_DQpwL
t_DAv
t_WRpwH
t_DQpwH
t_DAh
WAIT
Figure 13. Static Memory Burst Write Cycle Timing Measurement
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t_ADh
t_CSh
DS638PP4