CS4215 Datasheet, PDF (5/52 Pages) Cirrus Logic – 16-Bit Multimedia Audio Codec

CS4215
SWITCHING CHARACTERISTICS (T_A = 25°C; VA1, VA2, VD1, VD2 = +5V,
outputs loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = VD1, VD2)
Parameter
Symbol Min
Typ
Max Units
SCLK period
Master Mode, XCLK = 1 (Note 8) tsckw
- 1/(Fs*bpf) -
s
Slave Mode (XCLK = 0) tsckw
80
-
-
ns
SCLK high time
Slave Mode, XCLK = 0 (Note 9) tsckh
25
-
-
ns
SCLK low time
Slave Mode, XCLK = 0 (Note 9) tsckl
25
-
-
ns
Input Setup Time
Input Hold Time
Input Transition Time
ts1
15
-
-
ns
th1
10
-
-
ns
10% to 90% points
-
-
10
ns
Output delay
tpd1
-
-
28
ns
SCLK to TSOUT
tpd2
-
-
30
ns
Output to Hi-Z state
Output to non-Hi-Z
Input Clock Frequency
Timeslot 8, bit 0 thz
-
-
Timeslot 1, bit 7 tnz
15
-
Crystals
CLKIN (Note 10)
-
-
1.024
-
12
ns
-
ns
27
MHz
13.5 MHz
Input Clock (CLKIN) low time
30
-
-
ns
Input Clock (CLKIN) high time
30
-
-
ns
Sample rate
Fs
4
-
50
kHz
RESET low time
(Note 11)
500
-
-
ns
Notes: 8. In Master mode with BSEL1,0 set to 64 or 128 bits per frame (bpf), the SCLK duty cycle is 50%.
When BSEL1,0 is set to 256 bpf, SCLK will have the same duty cycle as CLKOUT.
See Internal Clock Generation section.
9. In Slave mode, FSYNC and SCLK must be derived from the master clock running the codec
(CLKIN, XTAL1, XTAL2).
10. Sample rate specifications must not be exceeded.
11. After powering up the CS4215, RESET should be held low for 50 ms to allow the voltage
reference to settle.
FSYNC _in
TSIN
t _s1
t _h1
t _s1
t _h1
TSOUT
t _pd2
t _pd2
FSYNC _out
SCLK
t _pd1
t _sckh
t _sckw
t _pd1
t _sckl
t _s1
t _h1
SDIN
SDOUT
DS76F2
t _nz
t _pd1
TS 1, Bit 7
TS 1, Bit 7
TS 1, Bit 6
t pd1
TS 1, Bit 6
TS 8, Bit 0
TS 8, Bit 0
t _hz
5