CS4215 Datasheet, PDF (43/52 Pages) Cirrus Logic – 16-Bit Multimedia Audio Codec

CDB4215
Speaker terminals are provided and are labeled
MOUT1 and MOUT2. Speakers connected to the
terminals must have an impedance of 32 Ω or
greater. DC blocking capacitors are included to
form a high-pass filter with the speaker imped-
ance. This filter blocks very low frequency
signals which can heavily distort some inexpen-
sive speakers.
SERIAL INTERFACE
The CDB4215 is primarily designed to evaluate
the CS4215 is single chip mode, i.e. only one
codec on the serial bus. This is the default state
for the CDB4215 and is defined by having the
P4 jumper in the "1CHIP" position, see Figure 4,
which connects FSYNC to TSIN. This connec-
tion defines the board codec’s time slots as the
first 64 bits of the frame. The only signals that
need to be connected to the DSP are the five sig-
nals on header J15. The serial interface is
illustrated in Figure 4.
If the goal is to connect multiple CDB4215s on
the same serial port, jumper P4 must be in the
"MULTI" position which disconnects TSIN from
FSYNC. The MULTI position also connects an
unbuffered SDOUT to header J14. This header
pin, SDOUTUB, must be used in lieu of
SDOUT since SDOUT is buffered and does not
go high impedance during other codec’s time
slots. Using the multi-chip scenario, the TSIN
header pin must be connected to the previous
codec’s TSOUT line and the first codec’s TSIN
must be connected, via the header, to FSYNC.
Note that when P4 is in the 1CHIP mode, the
SDOUTUB pin on header J14 is not connected
to the SDOUT pin on the CS4215 and is float-
ing.
There are two scenario’s that must be addressed
when connecting the CDB4215 to a DSP: one is
when the codec is the master in data mode and
the other is when the codec is a slave in data
DS76DB3
mode. In control mode the codec is always a
slave and FSYNC and SCLK must be driven
from the DSP. Since the evaluation board buffers
all the signals between the codec and the DSP,
the board must "know" which of the two modes
is being used. Jumper P3 selects the particular
mode.
Codec Master Data Mode
When the codec is to be programmed as a mas-
ter in data mode, the direction of FSYNC and
SCLK have to be changed between control mode
and data mode. In this case the P3 jumper must
be set for "M/S" which uses the D/C signal to
control the direction of the buffers (U7) for
SCLK and FSYNC. When P3 is set to M/S, the
buffers drive the J15 header in data mode and
receives FSYNC and SCLK from the header in
control mode.
Codec Slave Data Mode
When the codec is to be programmed as a slave
in data mode, FSYNC and SCLK are always in-
puts to the codec. In this mode P3 must be set to
"SLAVE" which configures the FSYNC and
SCLK buffers to always receive FSYNC and
SCLK from the J15 header.
As stated in the CS4215 data sheet, when the
codec is programmed in slave mode, XCLK = 0
in control mode, SCLK and FSYNC are inputs
and must be derived from the same clock used as
the master clock for the codec. Although SCLK
and FSYNC must be frequency locked to the
master clock, there is no phase requirement.
CONTROL PINS
All control pins, located on header J14, are de-
fined as pins that are not essential to the DSP
serial port when used in 1CHIP mode.
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