CS4215 Datasheet, PDF (34/52 Pages) Cirrus Logic – 16-Bit Multimedia Audio Codec

CS4215
SCLK - Serial Port Clock, Pin 43(L), 83(Q)
SCLK rising causes the data on SDOUT to be updated. SCLK falling latches the data on SDIN
into the CS4215. The SCLK signal can be generated off-chip, and input into the CS4215.
Alternatively, the CS4215 can generate and output SCLK in data mode.
FSYNC - Frame Sync Signal, Pin 42(L), 81(Q)
The Frame Synchronizing Signal is sampled by SCLK, with a rising edge indicating a new
frame is about to start. FSYNC frequency is always the system sample rate. Each frame may
have 64, 128 or 256 data bits, allowing for 1, 2 or 4 CS4215s connected to the same bus.
FSYNC may be input to the CS4215, or may be generated and output by the CS4215 in data
mode. When FSYNC is an input, it must be high for at least 1 SCLK period. FSYNC can stay
high for the rest of the frame, but must return low at least 2 SCLKs before the next frame starts.
TSIN - Time Slot Input, Pin 40(L), 77(Q)
TSIN high for at least 1 SCLK cycle indicates to the CS4215 that the next time slot is allocated
for it to use. TSIN is normally connected to the TSOUT pin of the previous device in the chain.
TSIN should be connected to FSYNC for the 1st (or only) CS4215 in the chain.
TSOUT - Time Slot Output, Pin 41(L), 79(Q)
TSOUT goes high for 1 SCLK cycle, indicating that the CS4215 is about to release the data
bus. Normally connected to the TSIN pin on the next device in the chain.
D/C - Data/Control Select Input, Pin 35(L), 70(Q)
When D/C is low, the information on SDIN and SDOUT is control information. When D/C is
high, the information on SDIN and SDOUT is data information.
PDN - Power Down Input, Pin 13(L), 16(Q)
When high, the PDN pin puts the CS4215 into the power down mode. In this mode HEADC
and CMOUT will not supply current. Power down causes all the control registers to change to
the default reset state. In the power down mode, the TSOUT pin remains active, and follows
TSIN delayed by less than 10 ns.
RESET - Active Low Reset Input, Pin 12(L), 14(Q)
Upon reset, the values of the control information (when D/C = 0) will be initialized to the
values given in the Reset Description section of this data sheet.
Clock and Crystal Pins
XTL1IN, XTL1OUT, XTL2IN, XTL2OUT - Crystals 1 and 2 Inputs and Outputs, Pins 6(L),
7(L), 10(L), 11(L), 97(Q), 2(Q), 8(Q), 10(Q)
Input and output connections for crystals 1 and 2. One of these oscillators may provide the
master clock to run the CS4215.
CLKIN - External Clock Input, Pin 4(L), 93(Q)
External clock input optionally used to clock the CS4215. The CLKIN frequency must be
256 times the maximum sample rate (FSYNC frequency).
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