CS4215 Datasheet, PDF (25/52 Pages) Cirrus Logic – 16-Bit Multimedia Audio Codec

CS4215
SDIN
DAD
DD
SDOUT
A/ µ
Decode
CS4215
D /A
A ttenuation
Digital-D igital
Loopback
M onitor = 1111
(Full Mute)
D ig ita l-
A n a lo g -
D ig ita l
Loopback
A/ µ
Encode
A/D
G a in
LOUT
ROUT
(S till O perate)
LIN
R IN
(D isconnected)
SDIN
(DAC data = 0)
0 is different for
each data
format
A/ µ
Decode
CS4215
D /A
A tte n u a tio n
Monitor = 0
LOUT
ROUT
SDOUT
A/ µ
Encode
A/D
G ain
ADA
LIN
R IN
Power Down Mode
Figure 16. DD, DAD & ADA Loopback Paths
LOOPBACK TEST MODES
Bringing the PDN pin high puts the CS4215 into
the power down mode. In this mode HEADC
and CMOUT will not supply current. Power
down will change all the control registers to the
reset state shown under each Control Time Slot
register. In the power down mode, the TSOUT
pin will follow the TSIN state with less than
10 ns delay.
The CS4215 contains three loopback modes that
may be used to test the codec. Two of the loop-
back test modes are designed to allow the host to
perform a self-test on the CS4215. The third
mode allows laboratory testing using external
equipment.
Host Self-Test Loopback Modes
After returning to normal operation from power
down, an offset calibration cycle must be exe-
cuted. Either bringing RESET low then high, or
updating the control registers, will cause an off-
set calibration cycle. In either case, a delay of
50 ms must occur after PDN goes low before
executing the offset calibration. This allows the
internal voltage reference time to settle.
Since the CS4215 is a mixed-signal device, it is
equipped with an internal register that will en-
able the host to perform a two-tiered test on
power-up or as needed. The loopback test is en-
abled by setting the Enable Loopback bit, ENL,
in control register 4. The first tier of loopback is
a digital-digital loopback, DD, which is selected
by clearing the DAD bit in control register 4 (see
DS76F2
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