CL-PS7110 Datasheet, PDF (5/82 Pages) Cirrus Logic – Low-Power System-on-a-Chip

CL-PS7110
Low-Power System-on-a-Chip
3.2.9 PEDR — Port E Data Register ......................................................................................... 42
3.2.10 PEDDR — Port E Data Direction Register ....................................................................... 42
3.2.11 SYSCON — System Control Register.............................................................................. 43
3.2.12 SYSFLG — System Status Flags Register ...................................................................... 45
3.2.13 MEMCFG1 — Memory Configuration Register 1 ............................................................. 47
3.2.14 MEMCFG2 — Memory Configuration Register 2 ............................................................. 47
3.2.15 DRFPR — DRAM Refresh Period Register...................................................................... 49
3.2.16 INTSR — Interrupt Status Register .................................................................................. 50
3.2.17 INTMR — Interrupt Mask Register ................................................................................... 52
3.2.18 LCDCON — LCD Control Register................................................................................... 52
3.2.19 TC1D — Timer Counter 1 Data Register.......................................................................... 53
3.2.20 TC2D — Timer Counter 2 Data Register.......................................................................... 53
3.2.21 RTCDR — Realtime Clock Data Register ........................................................................ 53
3.2.22 RTCMR — Realtime Clock Match Register...................................................................... 53
3.2.23 PMPCON — Pump Control Register................................................................................ 54
3.2.24 CODR — Codec Interface Data Register ......................................................................... 54
3.2.25 UARTDR — UART Data Register..................................................................................... 55
3.2.26 UBRLCR — UART Bit Rate and Line Control Register .................................................... 55
3.2.27 PALLSW Least-Significant Word-LCD Palette Register.................................................... 56
3.2.28 PALMSW Most-Significant Word-LCD Palette Register.................................................... 57
3.2.29 SYNCIO Synchronous Serial Interface Data Register...................................................... 58
3.2.30 STFCLR — Clear All Start Up Reason Flags Location .................................................... 58
3.2.31 BLEOI — Battery Low End of Interrupt............................................................................. 58
3.2.32 MCEOI — Media Changed End of Interrupt ..................................................................... 59
3.2.33 TEOI — Tick End of Interrupt Location............................................................................. 59
3.2.34 TC1EOI TC1 — End of Interrupt Location ........................................................................ 59
3.2.35 TC2EOI TC2 — End Of Interrupt Location ....................................................................... 59
3.2.36 RTCEOI — RTC Match End Of Interrupt.......................................................................... 59
3.2.37 UMSEOI — UART Modem Status Changed End of Interrupt........................................... 59
3.2.38 COEOI — Codec End of Interrupt Location...................................................................... 59
3.2.39 HALT — Enter Idle State Location.................................................................................... 59
3.2.40 STDBY — Enter Standby State Location ......................................................................... 59
4. ELECTRICAL SPECIFICATIONS .................................................................. 60
4.1 Absolute Maximum Ratings ................................................................................................. 60
4.2 Recommended Operating Conditions.................................................................................. 60
4.3 DC Characteristics............................................................................................................... 61
4.4 AC Characteristics ............................................................................................................... 62
4.5 I/O Buffer Characteristics..................................................................................................... 70
4.6 Test Modes........................................................................................................................... 70
4.6.1 Oscillator and PLL Bypass Mode ..................................................................................... 71
4.6.2 Functional (EPB) Test Mode ............................................................................................. 71
4.6.3 Oscillator and PLL Test Mode........................................................................................... 71
4.6.4 Pin Test Mode ................................................................................................................... 72
4.6.5 High-Z (System) Test Mode .............................................................................................. 73
4.6.6 Test ROM Mode................................................................................................................ 73
4.6.7 Software-Selectable Test Functionality ............................................................................. 74
5. PACKAGE SPECIFICATIONS........................................................................ 75
5.1 208-Pin VQFP Package Outline Drawing............................................................................. 75
May 1997
DATA BOOK v1.5
5
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