CL-PS7110 Datasheet, PDF (17/82 Pages) Cirrus Logic – Low-Power System-on-a-Chip

CL-PS7110
Low-Power System-on-a-Chip
EXPCLK
NCS 1111
CS 0000
1011
1111
1110
NMOE
NMWE
A ^000021C
0000000
0000001
0000002
0000003
0000220
WORD
D XXXXXXXX
XXXXXX67
XXXXXX45 XXXXXX23 XXXXXX01
EXPRDY
NOTE: A store of 0X0123456 is split into four 8-bit stores by CL-PS7110 hardware.
Figure 1-3. Word Write to 8-bit SRAM
1.2.5 Expansion and Memory Controller for SRAM/ROM/Flash Interface
Eight separate linear memory or expansion segments are decoded by the CL-PS7110. Each segment is
256 Mbytes in size and can be interfaced by using a conventional SRAM-like interface. Each segment can
be individually programmed to be 8, 16, or 32 bits wide, support Page mode access, and execute from
0–4 wait states. In addition, bus cycles can be extended using the EXPRDY input signal. Two segments
are allocated to ROM program segments and six to memory-mapped expansion. However, this is arbitrary
and can be redefined. Page mode access is accomplished by running up to four accesses together, this
can significantly improve bus bandwidth to devices, such as ROMs. Sequential Burst mode access is
always faulted (the bus returned to idle) after four accesses, regardless of bus width to allow DMA and
refresh cycles.
Each memory area has a single byte control register field, allowing the bus width and access timing to be
programmed. Refer to the description of MEMCFG1 and MEMCFG2 registers on page 47.
May 1997
DATA BOOK v1.5
17
FUNCTIONAL DESCRIPTION