CL-PS7110 Datasheet, PDF (28/82 Pages) Cirrus Logic – Low-Power System-on-a-Chip

CL-PS7110
Low-Power System-on-a-Chip
The system-only transitions to the operating state from the standby state if either the NEXTPWR or
BATOK, and the NPWRFL inputs are high. This prevents the system from attempting to start when the
power supply is inadequate (for example, when the main batteries are dead).
Figure 1-8 shows a state diagram for the CL-PS7110.
STANDBY
INTERRUPT OR RISING WAKEUP
WRITE TO STANDBY LOCATION, POWER FAIL
OR USER RESET
INTERRUPT, POWER FAIL
OR USER RESET
ACTIVE
WRITE TO HALT LOCATION
IDLE
Figure 1-8. State Diagram
1.2.20 Power Management
The CL-PS7110 is designed for battery-based hand-held organizers/PDAs and wireless communicators.
Minimizing power dissipation was a key design parameter. This required a holistic design approach in
which many power-saving features provide significant power reduction.
Low power consumption was also a key goal in the development and VLSI implementation of the
ARM710A core, cache and MMU.
Throughout the CL-PS7110, transition-avoidance techniques are used to minimize the power consump-
tion of CMOS switching currents. For example, clocks to unused peripherals are ‘gated-out’ at source
(where possible) rather than simply asserting the reset signal to the blocks. The main clock divider uses
ripple count stages where possible to generate clocks that are not required to be synchronous with the
main bus clock.
There are five FIFOs in the design. To save power and die area, a custom asynchronous ripple-through
design is employed. Parameterized gates are used in the ripple-through data-latching stages of the FIFO
(and in many places in the ARM710A) to optimize loading/drive ratios.
The on-chip oscillators and PLL save significant system power, removing the need for high-frequency
clocks on the main PCB. For memory and I/O devices that require clocking, CL-PS7110 can provide the
18.432-MHz master clock externally, but this is only enabled for the duration of the I/O cycle. The use of
a separate 32.768-kHz oscillator allows the Standby mode power consumption to be much lower than if
the 1-Hz clock has been divided-down from the main oscillator.
In normal operation, the display of video data on the LCD requires a significant proportion of system
power. To help minimize this, the DRAM row/column address lines are multiplexed-out in reverse order on
the high-order bits of the main address bus. This means that the most frequently changing address bits
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FUNCTIONAL DESCRIPTION
May 1997
DATA BOOK v1.5