CS4245 Datasheet, PDF (46/54 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC

CS4245
6.12 DAC Control 2 - Address 0Ch
7
DACSoft
6
DACZero
5
InvertDAC
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Active_H/L
6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods. See Table 17 on page 46.
Zero Cross Enable
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See Table 17 on page 46.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or
muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel. See Table 17 on page 46.
Table 17. DAC Soft Cross or Zero Cross Mode Selection
DACSoft
0
0
1
1
DACZeroCross
0
1
0
1
Mode
Changes to affect immediately
Zero Cross enabled
Soft Ramp enabled
Soft Ramp and Zero Cross enabled (default)
6.12.2 Invert DAC Output (Bit 5)
Function:
When this bit is set, the output of the DAC will be inverted.
6.12.3 Active High/Low (Bit 0)
Function:
When this bit is set, the INT pin will function as an active high CMOS driver.
When this bit is cleared, the INT pin will function as an active low open drain driver and will require an
external pull-up resistor for proper operation.
6.13 Interrupt Status - Address 0Dh
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
ADCClkErr
2
DACClkErr
1
ADCOvfl
0
ADCUndrfl
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once
since the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred
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