CS4245 Datasheet, PDF (35/54 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC

CS4245
will clock out the MSB of the addressed register (CDOUT will leave the high impedance state). If the MAP auto in-
crement bit is set to 1, the data for successive registers will appear consecutively.
CS
CCLK
C D IN
C H IP
ADDRESS
1001111
M AP
DATA
R/W
MSB
LSB
b y te 1 b y te n
CH IP
ADDRESS
1001111 _R/W
CDOUT
High Impedance
MSB
LSB MSB
LSB
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 17. Control Port Timing in SPI Mode
4.12.2 I²C Mode
In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no
CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be connected through
a resistor to VLC or DGND as desired. The state of the pins is sensed while the CS4245 is being reset.
The signal timings for a read and write cycle are shown in Figure 18 and Figure 19. A Start condition is defined as
a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All
other transitions of SDA occur while the clock is low. The first byte sent to the CS4245 after a Start condition consists
of a 7 bit chip address field and a R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field
are fixed at 10011. To communicate with a CS4245, the chip address field, which is the first byte sent to the CS4245,
should match 10011 followed by the settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the
operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or
written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto
increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an ac-
knowledge bit. The ACK bit is output from the CS4245 after each input byte is read, and is input to the CS4245 from
the microcontroller after each transmitted byte.
SCL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
SDA
1 0 0 1 1 AD1 AD0 0
INCR 6 5 4 3 2 1 0
76
ACK
ACK
10
76
ACK
10
START
Figure 18. Control Port Timing, I²C Write
DATA +n
76 10
ACK
STOP
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