CS4245 Datasheet, PDF (43/54 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC

CS4245
Table 11. MCLK2 Frequency
MCLK2 Divider
÷1
÷ 1.5
÷2
÷3
÷4
Reserved
Reserved
MCLK2 Freq2 MCLK2 Freq1 MCLK2 Freq0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
x
6.6 Signal Selection - Address 06h
7
Reserved
6
AOutSel1
5
AOutSel0
4
Reserved
3
Reserved
2
Reserved
1
LOOP
0
ASynch
6.6.1 Auxiliary Output Source Select (Bits 6:5)
Function:
These bits are used to select the analog output source. Please refer to Table 12 below.
Table 12. Auxiliary Output Source Selection
AOutSel1
0
0
1
1
AOutSel0
0
1
0
1
Auxiliary Output Source
High Impedance
DAC Output
PGA Output
Reserved
6.6.2 Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer
to “Internal Digital Loopback” on page 33.
6.6.3 Asynchronous Mode (Bit 0)
Function:
When this bit is set, the DAC and ADC may be operated at independent an asynchronous sample
rates derived from MCLK1 and MCLK2. When this bit is cleared, the DAC and ADC must operate at
synchronous sample rates derived from MCLK1.
6.7 Channel A PGA Control - Address 07h
7
Reserved
6
Reserved
5
Gain5
4
Gain4
3
Gain3
2
Gain2
1
Gain1
0
Gain0
6.7.1 Channel A PGA Gain (Bits 5:0)
Function:
See “Channel B PGA Gain (Bits 5:0)” on page 44.
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