CS4245 Datasheet, PDF (30/54 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC

CS4245
LRCK
(kHz)
32
44.1
48
64
88.2
96
128
176.4
192
Mode
64x
-
-
-
-
-
-
8.1920
11.2896
12.2880
96x
-
-
-
-
-
-
12.2880
16.9344
18.4320
128x
-
-
-
8.1920
11.2896
12.2880
16.3840
22.5792
24.5760
QSM
MCLK (MHz)
192x
256x
384x
512x
-
8.1920 12.2880 16.3840
-
11.2896 16.9344 22.5792
-
12.2880 18.4320 24.5760
12.2880 16.3840 24.5760 32.7680
16.9344 22.5792 33.8680 45.1584
18.4320 24.5760 36.8640 49.1520
24.5760 32.7680
-
-
33.8680 45.1584
-
-
36.8640 49.1520
-
-
DSM
768x
1024x
24.5760 32.7680
33.8680 45.1584
36.8640 49.1520
-
-
-
-
-
-
-
-
-
-
-
-
SSM
Table 2. Common Clock Frequencies
4.2.3 Master Mode
As a clock master, LRCK and SCLK will operate as outputs. The two serial ports may be independently placed into
Master or Slave mode. Each LRCK and SCLK is internally derived from its respective MCLK with LRCK equal to Fs
and SCLK equal to 64 x Fs as shown in Figure 13.
MCLK1 Freq Bits
MCLK1
÷1
000
÷1.5
001
÷2
010
÷3
011
÷4
100
MCLK2 Freq Bits
MCLK2
÷1
000
÷1.5
001
÷2
010
÷3
011
÷4
100
÷256
00
÷128
01
÷64
10
ADC_FM Bits
÷4
00
÷2
01
÷1
10
ASynch Bit
÷256
00
÷128
01
÷64
10
0
DAC_FM Bits
1
÷4
00
÷2
01
÷1
10
LRCK1
SCLK1
LRCK2
SCLK2
Figure 13. Master Mode Clocking
4.2.4 Slave Mode
In Slave mode, SCLK and LRCK operate as inputs. Each serial port may be independently placed into Slave mode.
The Left/Right clock signal must be equal to the sample rate, Fs. If operating in asynchronous mode, LRCK1 must
be synchronously derived from MCLK1 and LRCK2 must be synchronously derived from MCLK2. If operating in syn-
chronous mode, LRCK1, and LRCK2 must be synchronously derived from MCLK1. For more information on syn-
chronous and asynchronous modes, see “Synchronous / Asynchronous Mode” on page 29.
30