CS42438 Datasheet, PDF (45/64 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 8-out TDM CODEC

7.6 ADC CONTROL & DAC DE-EMPHASIS (ADDRESS 05H)
7
ADC1-2_HPF
FREEZE
6
ADC3_HPF
FREEZE
5
DAC_DEM
4
ADC1
SINGLE
3
ADC2
SINGLE
2
ADC3
SINGLE
1
AIN5_MUX
0
AIN6_MUX
7.6.1 ADC1-2 HIGH PASS FILTER FREEZE (ADC1-2_HPF FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC
offset value will be frozen and continue to be subtracted from the conversion result. See “ADC Digital
Filter Characteristics” on page 15.
7.6.2 ADC3 HIGH PASS FILTER FREEZE (ADC3_HPF FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter will be disabled for ADC3.The current DC offset value
will be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter Char-
acteristics” on page 15.
7.6.3 DAC DE-EMPHASIS CONTROL (DAC_DEM)
Default = 0
0 - No De-Emphasis
1 - De-Emphasis Enabled (Auto-Detect Fs)
Function:
Enables the digital filter to maintain the standard 15µs/50µs digital de-emphasis filter response at the
auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless
of this register setting, at any other sample rate.
7.6.4 ADC1 SINGLE-ENDED MODE (ADC1 SINGLE)
Default = 0
0 - Disabled; Differential input to ADC1
1 - Enabled; Single-Ended input to ADC1
Function:
When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC1.
+6 dB digital gain is automatically applied to the serial audio data of ADC1. The negative leg must be
driven to the common mode of the ADC. See Figure 21 on page 51 for a graphical description.
7.6.5 ADC2 SINGLE-ENDED MODE (ADC2 SINGLE)
Default = 0
0 - Disabled; Differential input to ADC2
1 - Enabled; Single-Ended input to ADC2
DS646PP2
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