CS42528 Datasheet, PDF(34/91 Page) Cirrus Logic – 114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

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CS42528 Datasheet, PDF (34/91 Pages) Cirrus Logic – 114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

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CS42528

4.6.4b OLM Config #2

This configuration will support up to 8 channels of DAC data, 6 channels of ADC data and no channels of

S/PDIF received data and will handle up to 20-bit samples at a sampling frequency of 96 kHz on all chan-

nels for both the DAC and ADC. The output data stream of the internal and external ADCs is configured

to use the SAI_SDOUT output and run at the SAI_SP clock speeds.

Functional Mode Register (addr = 03h)

Set CODEC_FMx = SAI_FMx = 00,01,10

Set ADC_SP SELx = 10

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Set ADC_OLx bits = 00,01,10

Set DAC_OLx bits = 00,01

Misc. Control Register (addr = 05h)

Set CODEC_SP M/S = 1

Set SAI_SP M/S = 1

Set EXT ADC SCLK = 1

Description

CX_LRCK must equal SAI_LRCK; sample rate conversion not supported

Configure ADC data to use SAI_SDOUT and SAI_SP Clocks. S/PDIF data

is not supported in this configuration

Select the digital interface format when not in one line mode

Select ADC operating mode, see table below for valid combinations

Select DAC operating mode, see table below for valid combinations

Set CODEC Serial Port to master mode.

Set Serial Audio Interface Port to master mode.

Identify external ADC clock source as CODEC Serial Port.

CX_SDOUT= not used

SAI_SDOUT=ADC Data

Not One

Line Mode

ADC Mode

One Line

Mode #1

One Line

Mode #2

Not One Line Mode

CX_SCLK=64 Fs

CX_LRCK=SSM/DSM/QSM

SAI_SCLK=64 Fs

SAI_LRCK=CX_LRCK

CX_SCLK=64 Fs

CX_LRCK=SSM/DSM

SAI_SCLK=128 Fs

SAI_LRCK=CX_LRCK

CX_SCLK=64 Fs

CX_LRCK=SSM

SAI_SCLK=256 Fs

SAI_LRCK=CX_LRCK

DAC Mode

One Line Mode #1

CX_SCLK=128 Fs

CX_LRCK=SSM

SAI_SCLK=64 Fs

SAI_LRCK=CX_LRCK

CX_SCLK=128 Fs

CX_LRCK=SSM

SAI_SCLK=128 Fs

SAI_LRCK=CX_LRCK

not valid

One Line Mode #2

not valid

LRCK

SCLK

MCLK

SDOUT1

SDOUT2

CS5361

RMCK

ADCIN1

ADCIN2

SAI_SCLK

SAI_LRCK

SAI_SDOUT

CX_SCLK

CX_LRCK

CX_SDOUT

CX_SDIN1

CX_SDIN2

CX_SDIN3

CX_SDIN4

CS42528

64Fs,128Fs,

256Fs

ADC Data

MCLK

SCLK_PORT1

LRCK_PORT1

SDIN_PORT1

64Fs,128Fs

SCLK_PORT2

LRCK_PORT2

SDIN_PORT2

SCLK_PORT3

LRCK_PORT3

SDOUT1_PORT3

SDOUT2_PORT3

SDOUT3_PORT3

SDOUT4_PORT3

DIGITAL AUDIO

PROCESSOR

Figure 17. OLM Configuration #2

DS586PP5

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