CS42528 Datasheet, PDF(33/91 Page) Cirrus Logic – 114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

CS42528 Datasheet, PDF (33/91 Pages) Cirrus Logic – 114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

◁

CS42528

4.6.4 One Line Mode(OLM) Configurations

4.6.4a OLM Config #1

One Line Mode Configuration #1 can support up to 8 channels of DAC data, 6 channels of ADC data and

2 channels of S/PDIF received data. This is the only configuration which will support up to 24-bit samples

at a sampling frequency of 48 kHz on all channels for both the DAC and ADC.

Functional Mode Register (addr = 03h)

Set CODEC_FMx = SAI_FMx = 00,01,10

Set ADC_SP SELx = 00

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Set ADC_OLx bits = 00,01,10

Set DAC_OLx bits = 00,01,10

Misc. Control Register (addr = 05h)

Set CODEC_SP M/S = 1

Set SAI_SP M/S = 1

Set EXT ADC SCLK = 0

Description

CX_LRCK must equal SAI_LRCK; sample rate conversion not supported

Configure ADC data on CX_SDOUT, S/PDIF data on SAI_SDOUT

Select the digital interface format when not in one line mode

Select ADC operating mode, see table below for valid combinations

Select DAC operating mode, see table below for valid combinations

Configure CODEC Serial Port to master mode.

Configure Serial Audio Interface Port to master mode.

Identify external ADC clock source as SAI Serial Port.

ADC Mode

Not One Line Mode

Not One

Line Mode

CX_SCLK=64 Fs

CX_LRCK=SSM/DSM/QSM

SAI_SCLK=64 Fs

SAI_LRCK=CX_LRCK

One Line

Mode #1

CX_SCLK=128 Fs

CX_LRCK=SSM/DSM

SAI_SCLK=64 Fs

SAI_LRCK=CX_LRCK

One Line

Mode #2

CX_SCLK=256 Fs

CX_LRCK=SSM

SAI_SCLK=64 Fs

SAI_LRCK=CX_LRCK

DAC Mode

One Line Mode #1

CX_SCLK=128 Fs

CX_LRCK=SSM/DSM

SAI_SCLK=64 Fs

SAI_LRCK=CX_LRCK

CX_SCLK=128 Fs

CX_LRCK=SSM/DSM

SAI_SCLK=64 Fs

SAI_LRCK=CX_LRCK

not valid

One Line Mode #2

not valid

CX_SCLK=256 Fs

CX_LRCK=SSM

SAI_SCLK=64 Fs

SAI_LRCK=CX_LRCK

LRCK

SCLK

MCLK

SDOUT1

SDOUT2

CS5361

MCLK

RMCK

ADCIN1

ADCIN2

SAI_SCLK

SAI_LRCK

SAI_SDOUT

CX_SCLK

CX_LRCK

CX_SDOUT

64Fs

SPDIF Data

64Fs,128Fs, 256Fs

ADC Data

SCLK_PORT1

LRCK_PORT1

SDIN_PORT1

SCLK_PORT2

LRCK_PORT2

SDIN_PORT2

CX_SDIN1

CX_SDIN2

CX_SDIN3

CX_SDIN4

CS42528

SCLK_PORT3

LRCK_PORT3

SDOUT1_PORT3

SDOUT2_PORT3

SDOUT3_PORT3

SDOUT4_PORT3

DIGITAL AUDIO

PROCESSOR

Figure 16. OLM Configuration #1

DS586PP5

▷