CS4365 Datasheet, PDF (32/51 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Channel D/A Converter

CS4365
3.14.3 SPI™ Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see Figure 25 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and
is used to control SPI writes to the control port. When the device detects a high to low transition on the
AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
3.14.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifi-
cations in Section 2.
1. Bring CS low.
2. The address byte on the CDIN pin must then be 00110000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see section 3.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then bring CS high.
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired,
bring CS high.
CS
CCLK
CDIN
CHIP
ADDRESS
MAP
DATA
0011000
R/W
MSB
LSB
byte 1 byte n
MAP = Memory Address Pointer
Figure 25. Control Port Timing, SPI mode
3.15 Memory Address Pointer (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
4
MAP4
0
3
MAP3
0
3.15.1 INCR (AUTO MAP INCREMENT ENABLE)
Default = ‘0’
0 - Disabled
1 - Enabled
2
MAP2
0
1
MAP1
0
0
MAP0
0
3.15.2 MAP4-0 (MEMORY ADDRESS POINTER)
Default = ‘00000’
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DS670PP1