CS4365 Datasheet, PDF (17/51 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Channel D/A Converter

CS4365
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, C_L = 30 pF)
Parameter
Symbol
Min
Max
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
(Note 17)
f_sclk
-
6
t_srs
500
-
t_spi
500
-
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
(Note 18)
t_csh
1.0
-
t_css
20
-
t_scl
66
-
t_sch
66
-
t_dsu
40
-
t_dh
15
-
Rise Time of CCLK and CDIN
(Note 19)
t_r2
-
100
Fall Time of CCLK and CDIN
(Note 19)
t_f2
-
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
Notes:
17. t_spi only needed before first falling edge of CS after RST rising edge. t_spi = 0 at all other times.
18. Data must be held for sufficient time to bridge the transition time of CCLK.
19. For F_SCK < 1 MHz.
RST
t _srs
CS
CCLK
CDIN
t _spi t _css
t _scl t _sch
t _r2
t _f2
t _{dsu t dh}
Figure 6. Control Port Timing - SPI Format
t _csh
DS670PP1
17