CS4222 Datasheet, PDF (22/26 Pages) Cirrus Logic – 20-Bit Stereo Audio Codec with Volume Control

CS4222
Analog Outputs
AOUTR-, AOUTR+ - Differential Right Channel Analog Outputs, Pins 23 and 24.
Analog output connections for the Right channel differential outputs. Nominally 2 Vrms
(differential) for full-scale digital input signal.
AOUTL-, AOUTL+ - Differential Left Channel Analog Outputs, Pins 25 and 26.
Analog output connections for the Left channel differential outputs. Nominally 2 Vrms
(differential) for full-scale digital input signal.
Digital Inputs
MCLK - Master Clock, Pin 3.
Clock source for the delta-sigma modulator sampling and digital filters. The frequency of this
clock must be either 256x, 384x, or 512x Fs.
LRCK - Left/Right Clock, Pin 4.
LRCK determines which channel, left or right, is to be input/output on SDIN/SDOUT.
Although the outputs for each ADC channel are transmitted at different times, Left/Right pairs
represent simultaneously sampled analog inputs. LRCK is an input clock whose frequency
must be equal to Fs.
SCLK - Serial Data Clock, Pin 5.
Clocks the individual bits of the serial data out from SDOUT and in from SDIN.
SDIN - Serial Data Input, Pin 9.
Two’s complement MSB-first serial data of either 16, 18, or 20 bits is input on this pin. The
data is clocked into the CS4222 via the SCLK clock and the channel is determined by the
LRCK clock. The default interface format on power-up is an I²S compatible 20-bit interface.
This may be changed by writing the control port (DSP Port Mode Byte #5).
DEM1, DEM0 - De-Emphasis Select, Pins 18 and 13.
Controls the activation of the standard 50/15 µs de-emphasis filter. 32, 44.1, or 48 kHz sample
rate selection defined in Table 4.
SMUTE - Soft Mute, Pin 2.
SMUTE low activates a muting function for both the left and right channel D/A converter
outputs. Soft muting is achieved by ramping down the volume in 0.5 dB steps until achieving
mute if SOFT bit (DAC Control Byte #2) is set to 0 (default).
Digital Outputs
SDOUT - Serial Data Output, Pin 8.
Two’s complement MSB-first serial data of 20 bits is output on this pin. The data is clocked
out via the SCLK clock and the channel is determined by LRCK.
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