CS4222 Datasheet, PDF (20/26 Pages) Cirrus Logic – 20-Bit Stereo Audio Codec with Volume Control

CS4222
Output Attenuator Data Byte (3, 4)
B7 B6 B5 B4 B3 B2 B1 B0
ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
ATT7-ATT0
Sets attenuator level
0 - No attenuation
227 - 113.5 dB attenuation
>227 - DAC muted
ATT0 represents 0.5 dB of attenuation
This register defaults to 00h.
DSP Port Mode Byte (5)
B7 B6 B5 B4 B3 B2 B1 B0
DEM2 DEM1 DEM0 DSCK DDO DDF2 DDF1 DDF0
DEM2-0
Selects de-emphasis control source
0 - De-emphasis controlled by pins
1 - 44.1 kHz de-emphasis setting
2 - 48 kHz de-emphasis setting
3 - 32 kHz de-emphasis setting
4 - De-emphasis disabled
5 - Not used
6 - Not used
7 - Not used
DSCK
DDO
Set the polarity of clocking data
0 - Data valid on rising edge of SCLK
1 - Data valid on falling edge of SCLK
Data output format
0 - I²S compatible
1 - Left justified
DDI2-DDI0
Data input format
0 - I²S compatible
1 - Left justified
2 - Right justified, 20-bit
3 - Right justified, 18-bit
4 - Right justified, 16-bit
5 - Not used
6 - Not used
7 - Not used
This register defaults to 00h.
Converter Status Report Byte (Read Only) (6)
B7 B6 B5 B4 B3 B2 B1 B0
ACCR ACCL LVR2 LVR1 LVR0 LVL2 LVL2 LVL0
ACCR-ACCL Acceptance bit
0 - ATT7-0 has been accepted
1 - New setting waiting for zero crossing
LVL2-0,LVR2-0 Left and Right ADC output level
0 - Normal output levels
1 - -6 dB level
2 - -5 dB level
3 - -4 dB level
4 - -3 dB level
5 - -2 dB level
6 - -1 dB level
7 - Clipping
LVL2-0 and LVR2-0 bits are ’sticky’. They constantly
monitor the ADC output for the peak levels and hold
the maximum output. They are reset to 0 when read.
This register is read only.
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DS236PP3