CS4222 Datasheet, PDF (19/26 Pages) Cirrus Logic – 20-Bit Stereo Audio Codec with Volume Control

CS4222
Memory Address Pointer (MAP)
B7 B6 B5 B4 B3 B2 B1 B0
INCR 0
0
0
0 MAP2 MAP1 MAP0
MAP2-MAP0 Register Pointer
INCR
Auto Increment Control Bit
0 - No auto increment
1 - Auto increment on
This register defaults to 00h.
Reserved Byte (0)
This byte is reserved for internal use and must
be set to 00h for normal operation.
This register defaults to 00h.
ADC Control Byte (1)
B7 B6 B5 B4 B3 B2 B1 B0
PDAD HPDR HPDL ADMR ADML CAL CALP CLKE
PDAD
Power Down ADC
0 - Normal
1 - Power down
HPDR-HPDL High pass filter defeat, right and left
0 - High pass filters active
1 - High pass filters defeated
ADMR-ADML ADC Muting, right and left
0 - Normal
1 - Output muted
CAL
Calibration control bit
0 - Normal operation
1 - Rising edge initiates calibration
The following bits are read only:
CALP
Calibration status
0 - Calibration done
1 - Calibration in progress
CLKE
Clocking Error
0 - No error
1 - error
This register defaults to 00h.
DAC Control Byte (2)
B7 B6 B5 B4 B3 B2 B1 B0
PDDA MUTC MUTR MUTL SOFT 0 RMP1 RMP0
PDDA
Power Down DAC
0 - Normal
1 - Power down
MUTC
Controls mute on consecutive zeros
function
0 - 512 consecutive zeros will mute DAC
1 - DAC output will not mute on zeros.
MUTR-MUTL
SOFT
Mute control bits
0 - Normal output level
1 - Selected DAC output muted
Soft Mute Control
0 - Volume control changes, muting and
mute-on-zeros occur with "ramp"
1 - Volume control changes, muting and
mute-on-zeros occur on zero crossings
RMP1-0
Soft Volume 0.5 dB step rate
0 - 1 step per 8 LRCK’s
1 - 1 step per 4 LRCK’s
2 - 1 step per 16 LRCK’s
3 - 1 step per 32 LRCK’s
This register defaults to 00h.
DS236PP3
19