CS4351 Datasheet, PDF (13/41 Pages) Cirrus Logic – 192 kHz STEREO DAC WITH 2 Vrms LINE OUT

CS4351
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VL, C_L = 20 pF)
Parameter
Symbol
Min
Max
CCLK Clock Frequency
f_sclk
-
6
RST Rising Edge to CS Falling
t_srs
500
-
CCLK Edge to CS Falling
(Note 8)
t_spi
500
-
CS High Time Between Transmissions
t_csh
1.0
-
CS Falling to CCLK Edge
t_css
20
-
CCLK Low Time
t_scl
66
-
CCLK High Time
t_sch
66
-
CDIN to CCLK Rising Setup Time
t_dsu
40
-
CCLK Rising to DATA Hold Time
(Note 9)
t_dh
15
-
Rise Time of CCLK and CDIN
(Note 10)
t_r2
-
100
Fall Time of CCLK and CDIN
(Note 10)
t_f2
-
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
Notes: 8. t_spi only needed before first falling edge of CS after RST rising edge. t_spi = 0 at all other times.
9. Data must be held for sufficient time to bridge the transition time of CCLK.
10. For F_SCK < 1 MHz.
RST
t _srs
CS
CCLK
C D IN
t _spi t _css
t _scl t _sch
t _csh
t _r2
t _f2
t _{dsu t dh}
Figure 3. Control Port Timing - SPI Format (Write)
DS566PP2
13