CS4351 Datasheet, PDF (11/41 Pages) Cirrus Logic – 192 kHz STEREO DAC WITH 2 Vrms LINE OUT

CS4351
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate (Manual selection)
Input Sample Rate (Auto selection)
LRCK Duty Cycle
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
Symbol
Single-Speed Mode Fs
Double-Speed Mode Fs
Quad-Speed Mode Fs
Single-Speed Mode Fs
Double-Speed Mode Fs
Quad-Speed Mode Fs
Single Speed Mode
Double Speed Mode
Quad Speed Mode
t_sclkl
t_sclkh
t_sclkw
t_sclkw
t_sclkw
t_slrd
t_slrs
t_sdlrs
t_sdh
Min
1.024
45
4
50
100
4
84
170
40
20
20
----------1-----------
( 128 ) F s
(^{---6---4--1--})^--F----s--
--------2---------
MCLK
20
20
20
20
Max
Units
51.2
MHz
55
%
50
kHz
100
kHz
200
kHz
50
kHz
100
kHz
200
kHz
60
%
-
ns
-
ns
-
-
-
-
-
-
-
ns
-
ns
-
ns
-
ns
LRCK
SCLK
SDATA
t _slrd
t _sdlrs
t _slrs
t _sclkh
t _sclkl
t _sdh
Figure 1. Serial Input Timing
DS566PP2
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