CS4351 Datasheet, PDF (12/41 Pages) Cirrus Logic – 192 kHz STEREO DAC WITH 2 Vrms LINE OUT

CS4351
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VL, C_L = 20 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
f_scl
-
100
kHz
RST Rising Edge to Start
t_irs
500
-
ns
Bus Free Time Between Transmissions
t_buf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
-
µs
Clock Low time
t_low
4.7
-
µs
Clock High Time
t_high
4.0
-
µs
Setup Time for Repeated Start Condition
t_sust
4.7
-
µs
SDA Hold Time from SCL Falling
(Note 7)
t_hdd
0
-
µs
SDA Setup time to SCL Rising
t_sud
250
-
ns
Rise Time of SCL and SDA
t_rc, t_rc
-
1
µs
Fall Time SCL and SDA
t_fc, t_fc
-
300
ns
Setup Time for Stop Condition
t_susp
4.7
-
µs
Acknowledge Delay from SCL Falling
t_ack
300
1000
ns
Notes: 7. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
RST
SDA
SCL
t _irs
S to p
S tart
t _buf
t _hdst
t
lo w
t _high
R epe ate d
S ta rt
t _rd
t _hdst
t _fc
t
hdd
t _sud
t _ack
t _sust
t _rc
Figure 2. Control Port Timing - I²C Format
S to p
t _fd
t _susp
12
DS566PP2