SHC605 Datasheet, PDF (12/15 Pages) Burr-Brown (TI) – High-Speed Operational TRACK-AND-HOLD AMPLIFIER

will depend on the ADC conversion time. In this application
the one-shot is used to set the critical ADC timing which
means the user has more freedom in selecting the convert
command duty cycle. Since the convert command is applied
directly to the SHC605—instead of after additional logic
and clock conditioning—aperture jitter noise is minimized.
OFFSET VOLTAGE ADJUSTMENT
The SHC605’s input offset voltage is laser-trimmed and will
require no further adjustment for most applications. How-
ever, if additional adjustment is needed, the circuit in Figure
8 can be used without degrading offset drift with tempera-
ture. Avoid external adjustment whenever possible since
extraneous noise, such as power supply noise, can be inad-
vertently coupled into the amplifier’s inverting input. Re-
member that additional offset errors can be created by the
amplifier’s input bias currents. Whenever possible, match
the impedance seen by both inputs as is shown with R₃. This
will reduce input offset voltage errors due to the amplifier’s
input offset current, which is typically only 0.2µA.
+V_CC
20kΩ
R_TRIM
47kΩ
–V_CC
R₂
8
9
1 ^SHC605
R₁
R₃ = R₁ || R₂₍₁₎
V_IN or Ground
Output
Trim
Range
≈
+V_CC
R₂
R_TRIM
to
–V_CC
R₂
R_TRIM
NOTE: (1) R₃ is optional and can be used to cancel
offset errors due to input bias currents.
FIGURE 8. Offset Voltage Trim.
damage can cause subtle changes in SHC605 input charac-
teristics without necessarily destroying the device. In preci-
sion track-and-hold amplifiers, this may cause a noticeable
degradation in performance. Therefore, static protection is
recommended when handling the SHC605.
External
Pin
+V_{CC ESD Protection Diodes Internally}
Connected to All Pins
Internal
Circuitry
–V_CC
FIGURE 9. Internal ESD Protection.
LAYOUT AND BYPASSING
For best performance, good high speed design techniques
must be applied. The component (top) side ground plane
should be as large as possible and continuous (not frag-
mented). Two ounce copper cladding is recommended.
All traces should be as short as possible, especially the
output. As much of the ground plane as possible should be
removed from around the +In, –In, and V_OUT pins to reduce
parasitic capacitance and minimize coupling onto the analog
signal path.
Power supply decoupling capacitors must be used as shown
in Figures 3 through 6. The 0.01µF capacitors should be low
inductance surface mount devices and should be connected
as close to the SHC605 ±Vs leads as possible (within 30
mils). The 1µF low frequency bypass capacitors should be
tantalum capacitors (preferably surface mount) and should
be located within one inch of the SHC605. Surface mount
resistors are also recommended and should be placed as
close to the SHC605 as possible to minimize inductance.
CAPACITIVE LOADS
The SHC605’s output stage has been optimized to drive
resistive loads as low as 50Ω. Capacitive loads will decrease
the amplifier’s phase margin which may cause high fre-
quency peaking or oscillations. Capacitive loads greater than
10pF should be buffered by connecting a small resistance,
usually 20Ω to 50Ω, in series with the output as shown in
INPUT PROTECTION
The SHC605 incorporates on-chip ESD protection diodes as
shown in Figure 9. All pins on the SHC605 are internally
protected from ESD by means of a pair of back-to-back
reverse-biased diodes to either power supply as shown.
These diodes will begin to conduct when the input voltage
exceeds either power supply by about 0.7V. This situation
can occur with loss of the amplifier’s power supplies while
a signal source is still present. The diodes can typically
withstand a continuous current of 30mA without destruc-
tion. To insure long term reliability diode current should be
externally limited to 10mA or so whenever possible. Static
(R_S is typically 20Ω to 50Ω)
8
R_S
1 ^SHC605 9
R_L
C_L
FIGURE 10. Driving Capacitance Load.
®
SHC605
12