DEMO-ATF-5X143 Datasheet, PDF (11/16 Pages) Broadcom Corporation. – Low Noise Enhancement Mode Pseudomorphic HEMT in a Surface Mount Plastic Package

I_BB is the current flowing through the R1/R2 resistor
voltage divider network.
The values of resistors R1 and R2 are calculated with the
following formulas
R1 = V_gs (2)
I_BB ^p
R2 = ^(Vds ^{– V}gs^{) R1} (3)
V_gs
Example Circuit
V_DD = 5 V
V_ds = 3V
I_ds = 60 mA
V_gs = 0.59V
Choose I_BB to be at least 10X the normal expected gate
leakage current. I_BB was chosen to be 2 mA for this
example. Using equations (1), (2), and (3) the resistors
are calculated as follows
R1 = 295
R2 = 1205
R3 = 32.3
Active Biasing
Active biasing provides a means of keeping the
quiescent bias point constant over temperature and
constant over lot to lot variations in device dc per-
formance. The advantage of the active biasing of an
enhancement mode PHEMT versus a depletion mode
PHEMT is that a negative power source is not required.
The techniques of active biasing an enhancement
mode device are very similar to those used to bias a
bipolar junction transistor.
INPUT
C1
Q1
Zo
L1
L2
C2
R5
C3
R6
C7
Q2
R7
R1
C4
OUTPUT
Zo
L4
L3
C5
R4
C6
Vdd
R3
R2
Figure 24. Typical ATF-54143 LNA with Active Biasing.
An active bias scheme is shown in Figure 24. R1 and
R2 provide a constant voltage source at the base of a
PNP transistor at Q2. The constant voltage at the base
of Q2 is raised by 0.7 volts at the emitter. The constant
emitter voltage plus the regulated V_DD supply are
present across resistor R3. Constant voltage across R3
provides a constant current supply for the drain current.
Resistors R1 and R2 are used to set the desired Vds. The
11
combined series value of these resistors also sets the
amount of extra current consumed by the bias network.
The equations that describe the circuit’s operation are
as follows.
V_E = V_ds + (I_ds • R4) (1)
R3 = ^{VDD – VE}
(2)
I_ds ^p
V_B = V_E – V_BE
(3)
V_B =
R1
R1 + R2 ^{p VDD}
(4)
V_DD = I_BB (R1 + R2) (5)
Rearranging equation (4) provides the following
formula:
R2 = ^{R1 (VDD – VB) (4A)}
V_B
and rearranging equation (5) provides the following
formula:
V_DD
(5A)
R1 =
( ) 9
I_BB 1 + V_DD – V_B
p
V_B
Example Circuit
V_DD = 5V
V_ds = 3V
I_ds = 60 mA
R4 = 10
V_BE = 0.7 V
Equation (1) calculates the required voltage at the
emitter of the PNP transistor based on desired V_ds and
I_ds through resistor R4 to be 3.6V. Equation (2) calcu-
lates the value of resistor R3 which determines the
drain current I_ds. In the example R3=23.3. Equation
(3) calculates the voltage required at the junction of
resistors R1 and R2. This voltage plus the step-up of
the base emitter junction determines the regulated
V_ds. Equations (4) and (5) are solved simultaneously
to determine the value of resistors R1 and R2. In the
example R1=1450 and R2=1050. R7 is chosen to
be 1k. This resistor keeps a small amount of current
flowing through Q2 to help maintain bias stability. R6 is
chosen to be 10k. This value of resistance is necessary
to limit Q1 gate current in the presence of high RF drive
level (especially when Q1 is driven to P_1dB gain com-
pression point).