HCPL-0872-000E Datasheet, PDF (8/12 Pages) AVAGO TECHNOLOGIES LIMITED – Digital Interface IC

Serial Configuration Timing
The HCPL-0872 Digital Interface IC is programmed using
the Serial Configuration Interface (SCI), which consists of
the clock (CCLK), data (CDAT), and enable/latch (CLAT)
signals. Figure 3 illustrates the timing for the serial con-
figuration interface. To send a byte of configuration data
to the HCPL-0872, first bring CLAT low. Then clock in the
eight bits of the configuration byte (MSB first) using CDAT
and the rising edge of CCLK. After the last bit has been
clocked in, bringing CLAT high again will latch the data
into the appropriate configuration register inside the
interface IC. If more than eight bits are clocked in before
CLAT is brought high, only the last eight bits will be used.
Refer to the Digital Interface Configuration section to
determine appropriate configuration data. If the default
configuration of the digital interface IC is acceptable,
then CCLK, CDIN and CLAT may be connected to either
V_DD or GND.
Channel Select Timing
The channel select signal (CHAN) determines which input
channel will be used for the next conversion cycle. A logic
low level selects channel one, a high level selects channel
2. CHAN should not be changed during a conversion
cycle. The state of the CHAN signal has no effect on the
behavior of either the over-range detection circuit (OVR1)
or the adjustable threshold detection circuit (THR1). Both
OVR1 and THR1 continuously monitor channel 1 inde-
pendent of the CHAN signal. CHAN also does not affect
the behavior of the pre-trigger circuit, which is tied to
the conversion timing of channel 1, as explained in the
Digital Interface Configuration section.
CLAT
t _SUCL1
t _SUCL2
CDAT
B7
B6 B5 B4 B3 B2 B1 B0
t _SUCLK
CCLK
t _HDCLK
t _PWH
t _PWL
t _PER
Figure 3. Serial Configuration Interface Timing.