HCPL-0872-000E Datasheet, PDF (5/12 Pages) AVAGO TECHNOLOGIES LIMITED – Digital Interface IC

Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Supply Voltage
Input Voltage
Output Voltage
Lead Solder Temperature
Solder Reflow Temperature Profile
Symbol Min.
Max.
Units
T_S
-55
125
°C
T_A
-40
85
°C
V_DD
0
5.5
V
All Inputs -0.5
V_DD + 0.5 V
All Outputs -0.5
V_DD + 0.5 V
260°C for 10 sec., 1.6 mm below seating plane
See Reflow Thermal Profile
Notes 1. Avago Technologies recommends the use of non-chlorinated solder fluxes.
Note
1
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Supply Voltage
Input Voltage
Symbol
T_A
V_DD
All Inputs
Min.
-40
4.5
0
Max.
85
5.5
V_DD
Units
°C
V
V
Electrical Specifications (DC)
Unless otherwise noted, all Typical specifications are at T_A = 25°C and V_DD = 5 V, and all Minimum and Maximum
specifications apply over the following ranges: T_A = -40°C to +85°C and V_DD = 4.5 to 5.5 V.
Parameter
Symbol Min. Typ. Max. Units Test Conditions Fig.
Supply Current
DC Input Current
Input Logic Low Voltage
Input Logic High Voltage
Output Logic Low Voltage
Output Logic High Voltage
Clock Frequency
(CCLK, MCLK and SCLK)
I_DD
3
5
mA f_CLK = 10 MHz
I_IN
0.001 10
µA
V_IL
0.8
V
V_IH
3.6
V
V_OL
0.15
0.4
V
I_OUT = 4 mA
V_OH
4.3 5.0
V
I_OUT = -400 µA
f_CLK
20
MHz
Clock Period (CCLK, MCLK and SCLK) t_PER
50
ns
2, 3
Clock High Level Pulse Width
t_PWH
20
ns
2, 3
(CCLK, MCLK and SCLK)
Clock Low Level Pulse Width
t_PWL
20
ns
2, 3
(CCLK, MCLK and SCLK)
Setup Time from DAT to Rising Edge t_SUCLK 10
ns
2
of CLK (CDAT, CCLK, MDAT and MCLK)
DAT Hold Time after Rising Edge
t_HDCLK 10
ns
2
of CLK (CDAT, CCLK, MDAT and MCLK)
Setup Time from Falling Edge
t_SUCL1 20
ns
2
of CLAT to First Rising Edge of CCLK
Setup Time from Last Rising
t_SUCL2 20
ns
2
Edge of CCLK to Rising Edge of CLAT
Delay Time from Falling
t_DSDAT
15
ns
3
Edge of SCLK to SDAT
Setup Time from Data
t_SUS
200
ns
3
Ready to First Falling Edge of SCLK
Setup Time from CHAN
t_SUCHS 20
ns
to falling edge of CS
Reset High Level Pulse Width
t_PWR
100
ns
Notes:
1. Avago Technologies recommends the use of non-chlorinated solder fluxes.