HCPL-M454 Datasheet, PDF (7/12 Pages) Agilent(Hewlett-Packard) – Ultra High CMR, Small Outline, 5 Lead, High Speed Optocoupler

Notes:
  1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C.
  2. Derate linearly above 70°C free-air temperature at a rate of 1.6mA/°C.
  3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mA/°C.
  4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mA/°C.
  5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (I_O), to the forward LED input current (I_F), times 100.
  6. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together.
  7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dV_CM/dt on
the leading edge of the common mode pulse, V_CM, to assure that the output will remain in a Logic High state (i.e., V_O > 2.0 V). Common mode
transient immunity in a Logic Low level is the maximum tolerable (negative) dV_CM/dt on the trailing edge of the common mode pulse signal,
V_CM, to assure that the output will remain in a Logic Low state (i.e., V_O < 0.8 V).
  8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maxi-
mum tolerable dV_CM/dt on the leading edge of the common mode pulse, V_CM, to assure that the output will remain in a Logic High state (i.e.,
V_O > 3.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable dV_CM/dt on the trailing edge of the common
mode pulse signal,V_CM, to assure that the output will remain in a Logic Low state (i.e., V_O < 1.0 V).
  9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
10. The R_L = 20 kΩ, C_L = 100 pF load represents an IPM (Intelligent Power Mode) load.
11. Use of a 0.1 µF bypass capacitor connected between pins 4 and 6 is recommended.
12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V_RMS for 1 second (leakage detec-
tion current limit, I_i-e ≤ 5 µA).
13. The difference between t_PLH and t_PHL, between any two HCPL-M454 parts under the same test condition. (See Power Inverter Dead Time and
Propagation Delay Specifications section).
T_A = 25°C
10 _{VCC = 5.0 V}
40 mA
35 mA
30 mA
25 mA
5
20 mA
15 mA
10 mA
I_F = 5 mA
0
0
10
20
V_O – OUTPUT VOLTAGE – V
1.5
1.0
0.5
NORMALIZED
I_F = 16 mA
V_O = 0.4 V
V_CC = 5.0 V
T_A = 25°C
0.0
0 2 4 6 8 10 12 14 16 18 20 22 24 26
I_F – INPUT CURRENT – mA
1000
100
I_F
10
+
V_F
–
1.0
T_A = 25°C
0.1
0.01
0.001
1.1 1.2 1.3 1.4 1.5 1.6
V_F – FORWARD VOLTAGE – VOLTS
Figure 1. DC and Pulsed Transfer Characteristics.
Figure 2. Current Tra_Hns_Cfe_Pr_LR_-a_Mt₄io₅v₄s._fiI_gnp₂ut Current.
Figure 3. Input Current vs. Forward Voltage.
HCPL-M454 fig 1
HCPL-M454 fig 3
1.1
1.0
0.9
NORMALIZED
I_F = 16 mA
0.8
V_O = 0.4 V
V_CC = 5.0 V
T_A = 25°C
0.7
0.6
-60 -40 -20 0 20 40 60 80 100 120
T_A – TEMPERATURE – °C
10 ⁴
10 ³
I_F = 0 mA
10 ²
V_O = V_CC = 5.0 V
10 ¹
10 ⁰
10^-1
10^-2
-60 -40 -20 0 20 40 60 80 100 120
T_A – TEMPERATURE – °C
Figure 4. Current Transfer Ratio vs. Temperature.
HCPL-M454 fig 4
Figure 5. Logic High Output Current vs. Temperature.
HCPL-M454 fig 5