HCTL-2001-A00 Datasheet, PDF (6/16 Pages) AVAGO TECHNOLOGIES LIMITED – Quadrature Decoder/Counter Interface ICs

Switching Characteristics
Table 5. Switching Characteristics Max/Min specifications at V_DD = 5.0 ± 5%, T_A = -40 to +85 ^OC, C_L = 40 pf
Symbol Description
Min. Max.
1 tCLK Clock Period
70
2 tCHH Pulse width, clock high
28
3 tCD Delay time, rising edge of clock to valid, updated count information on
65
D0-7
4 tODE Delay time, OE fall to valid data
65
5 tODZ Delay time, OE rise to Hi-Z state on D0-7
40
6 tSDV Delay time, SEL valid to stable, selected data byte (delay to High Byte
65
= delay to Low Byte)
7 tCLH Pulse width, clock low
28
8 tSS Setup time, SEL before clock fall
20
9 tOS Setup time, OEN before clock fall
20
10 tSH Hold time, SEL after clock fall
0
11 tOH Hold time, OE after clock fall
0
12 tRST Pulse width, RST low
28
13 tDCD Hold time, last position count stable on D0-7 after clock rise
10
14 tDSD Hold time, last data byte stable after next SEL state change
10
15 tDOD Hold time, data byte stable after OE rise
10
16 tUDD Delay time, U/D valid after clock rise
45
17 tCHD Delay time, CNTDCDR or CNTCAS high after clock rise
45
18 tCLD Delay time, CNTDCDRor CNTCAS low after clock fall
45
19 tUDH Hold time, U/D stable after clock rise
10
20 tUDCS Setup time, U/D valid before CNTDCDR or CNTCAS rise
tCLK-45
21 tUDCH Hold time, U/D stable after CNTDCDR or CNTCAS rise
tCLK-45
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 1. Reset Waveform
Figure 2: Waveforms for Positive Clock Edge Related Delays
6