HCTL-2001-A00 Datasheet, PDF (5/16 Pages) AVAGO TECHNOLOGIES LIMITED – Quadrature Decoder/Counter Interface ICs

Table 4b. Functional Pin Descriptions (PLCC Package)
Symbol
VDD
VSS
CLK
CHA
CHB
RST
OE
SEL
Pin
Description
HCTL HCTL
2017-PLC 2021-PLC
20
20
Power Supply
10
10
Ground
2
2
CLK is a Schmitt-trigger input for the external clock signal.
9
9
CHA and CHB are Schmitt-trigger inputs that accept the outputs from a
8
8
quadrature-encoded source, such as incremental optical shaft encoder. Two
channels, A and B, nominally 90 degrees out of phase, are required.
7
7
This active low Schmitt-trigger input clears the internal position counter and the
position latch. It also resets the inhibit logic. RST is asynchronous with respect
to any other input signals.
4
4
This CMOS active low input enables the tri-state output buffers. The OE/ and SEL
inputs are sampled by the internal inhibit logic on the falling edge of the clock to
control the loading of the internal position data latch.
3
3
These CMOS inputs directly controls which data byte from the position latch is
enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL also control
the internal inhibit logic.
SEL
BYTE SELECTED
0
High
1
Low
CNTDCDR NA
16
U/D
NA
5
CNTCAS NA
15
D0
1
1
D1
19
19
D2
18
18
D3
17
17
D4
14
14
D5
13
13
D6
12
12
D7
11
11
A pulse is presented on this LSTTL-compatible output when the quadrature
decoder has detected a state transition.
This LSTTL-compatible output allows the user to determine whether the IC is
counting up or down and is intended to be used with the CNTDCDR and CNTCAS
outputs. The proper signal U (high level) or D/ (low level) will be present before
the rising edge of the CNTDCDR and CNTCAS outputs.
A pulse is presented on this LSTTL-compatible output when the HCTL-2021-PLC
internal counter overflows or underflows. The rising edge on this waveform may
be used to trigger an external counter.
These LSTTL-compatible tri-state outputs form an 8-bit output ports through which
the contents of the 16-bit position latch may be read in 2 sequential bytes. The
High byte is read first followed by the Low bytes.
5