HCTL-2001-A00 Datasheet, PDF (4/16 Pages) AVAGO TECHNOLOGIES LIMITED – Quadrature Decoder/Counter Interface ICs

Functional Pin Description
Table 4a. Functional Pin Descriptions (PDIP Package)
Symbol
VDD
VSS
CLK
CHA
CHB
Pin
HCTL-
2001-
A00
16
8
2
76
RST
5
OE
4
SEL
3
HCTL-
2017-
A00
16
8
2
76
5
4
3
HCTL-
2021-
A00
20
10
2
98
7
4
3
Description
Power Supply
Ground
CLK is a Schmitt-trigger input for the external clock signal.
CHA and CHB are Schmitt-trigger inputs that accept the outputs from a
quadrature-encoded source, such as incremental optical shaft encoder. Two
channels, A and B, nominally 90 degrees out of phase, are required.
This active low Schmitt-trigger input clears the internal position counter and
the position latch. It also resets the inhibit logic. RST is asynchronous with
respect to any other input signals.
This CMOS active low input enables the tri-state output buffers. The OE/
and SEL inputs are sampled by the internal inhibit logic on the falling edge
of the clock to control the loading of the internal position data latch.
These CMOS inputs directly controls which data byte from the position latch
is enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL also
control the internal inhibit logic.
SEL
BYTE SELECTED
0
High
1
Low
CNT_DCDR NA
NA
16
U/D
NA
NA
5
CNTCAS NA
NA
15
D0
1
1
1
D1
15
15
19
D2
14
14
18
D3
13
13
17
D4
12
12
14
D5
11
11
13
D6
10
10
12
D7
9
9
11
NC
NA
NA
6
A pulse is presented on this LSTTL-compatible output when the quadrature
decoder has detected a state transition. CNT
This LSTTL-compatible output allows the user to determine whether the IC
is counting up or down and is intended to be used with the CNTDCDR and
CNTCAS outputs. The proper signal U (high level) or D/ (low level) will be
present before the rising edge of the CNTDCDR and CNTCAS outputs.
A pulse is presented on this LSTTL-compatible output when the HCTL-2021-
A00 internal counter overflows or underflows. The rising edge on this
waveform may be used to trigger an external counter.
These LSTTL-compatible tri-state outputs form an 8-bit output ports through
which the contents of the 16-bit position latch may be read in 2 sequential
bytes. The High byte is read first followed by the Low bytes.
Not connected - this pin should be left floating.
4