HDSP-2533 Datasheet, PDF (5/15 Pages) AVAGO TECHNOLOGIES LIMITED – Eight Character 5 mm Smart Alphanumeric Display

AC Timing Characteristics over Temperature Range
V_DD = 4.5 to 5.5 V unless otherwise specified.
Reference
Number
Symbol Description
Min.^[1]
Units
1
t_ACC
Display Access Time
  Write
  Read
210
230
ns
2
t_ACS
Address Setup Time to Chip Enable
3
t_CE
Chip Enable Active Time^{[2, 3]}
  Write
  Read
10
ns
140
160
ns
4
t_ACH
Address Hold Time to Chip Enable
20
ns
5
t_CER
Chip Enable Recovery Time
6
t_CES
Chip Enable Active Prior to Rising Edge of^{[2, 3]}
  Write
  Read
60
ns
140
160
ns
7
t_CEH
Chip Enable Hold Time to Rising Edge of Read/Write Signal^[2,3]
0
ns
8
t_W
Write Active Time
100
ns
9
t_WD
Data Valid Prior to Rising Edge of Write Signal
10
t_DH
Data Write Hold Time
50
ns
20
ns
11
t_R
Chip Enable Active Prior to Valid Data
160
ns
12
t_RD
Read Active Prior to Valid Data
75
ns
13
t_DF
Read Data Float Delay
10
ns
t_RC
Reset Active Time^[4]
300
ns
Notes:
1.  Worst case values occur at an IC junction temperature of 125°C.
2.  For designers who do not need to read from the display, the Read line can be tied to V_DD and the Write and Chip Enable lines can be tied
together.
3.  Changing the logic levels of the Address lines when CE = “0” may cause erroneous data to be entered into the Character RAM, regardless of the
logic levels of the WR and RD lines.
4.  The display must not be accessed until after 3 clock pulses (110 µs min. using the internal refresh clock) after the rising edge of the reset line.
Symbol Description
F_OSC
Oscillator Frequency
F_RF[5]
Display Refresh Rate
F_FL[6]
Character Flash Rate
t_ST[7]
Self Test Cycle Time
Notes:
5.  F_RF = F_OSC/224.
6.  F_FL = F_OSC/28,672.
7.  t_ST = 262,144/F_OSC.
25°C Typical
57
256
2
4.6
Minimum^[1]
28
128
1
9.2
Units
kHz
Hz
Hz
sec