HDSP-2533 Datasheet, PDF (10/15 Pages) AVAGO TECHNOLOGIES LIMITED – Eight Character 5 mm Smart Alphanumeric Display

UDC RAM and UDC Address Register
Figure 3 shows the logic levels needed to access the UDC
RAM and the UDC Address Register. The UDC Address
Register is eight bits wide. The lower four bits (D₀-D₃) are
used to select one of the 16 UDC locations. The upper four
bits (D₄-D₇) are not used. Once the UDC address has been
stored in the UDC Address Register, the UDC RAM can be
accessed.
To completely specify a 5 x 7 character requires eight write
cycles. One cycle is used to store the UDC RAM address in
the UDC Address Register. Seven cycles are used to store
dot data in the UDC RAM. Data is entered by rows. One
cycle is needed to access each row. Figure 4 shows the
organization of a UDC character assuming the symbol to
be stored is an “F.” A₀-A₂ are used to select the row to be
accessed and D₀-D₄ are used to transmit the row dot data.
The upper three bits (D₅-D₇) are ignored. D₀ (least signif­i­
cant bit) corresponds to the right most column of the 5 x 7
matrix and D₄ (most significant bit) corresponds to the left
most column of the 5 x 7 matrix.
RST CE WR RD
0 0 UNDEFINED
1
0
0
1
1 WRITE TO DISPLAY
0 READ FROM DISPLAY
1 1 UNDEFINED
CONTROL SIGNALS
FL A₄ A₃ A₂ A₁ A₀
10 0X XX
UDC ADDRESS REGISTER ADDRESS
D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀
XXXX
UDC CODE
UDC ADDRESS REGISTER DATA FORMAT
RST CE WR RD
0 0 UNDEFINED
1
0
0
1
1 WRITE TO DISPLAY
0 READ FROM DISPLAY
1 1 UNDEFINED
CONTROL SIGNALS
Flash RAM
Figure 5 shows the logic levels needed to access the Flash
RAM. The Flash RAM has one bit associated with each
location of the Character RAM. The Flash input is used
to select the Flash RAM. Address lines A₃-A₄ are ignored.
Address lines A₀-A₂ are used to select the location in the
Flash RAM to store the attri­bute. D₀ is used to store or
remove the flash attribute. D₀ = “1” stores the attribute
and D₀ = “0” removes the attribute.
When the attribute is enabled through bit 3 of the Control
Word and a “1” is stored in the Flash RAM, the correspond-
ing character will flash at approximately 2 Hz. The actual
rate is dependent on the clock fre­quency. For an external
clock the flash rate can be calculated by dividing the clock
frequency by 28,672.
CCCCC
OOOOO
LLLLL
12345
D₄ D₃ D₂ D₁ D₀
11111
10000
10000
11110
10000
10000
10000
IGNORED
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
ROW 7
UDC CHARACTER
•••••
•
•
••••
•
•
•
HEX CODE
1F
10
10
1E
10
10
10
0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED
Figure 4. Data to load “”F’’ into the UDC RAM.
FL A₄ A₃
101
UDC RAM ADDRESS
A₂ A₁ A₀
ROW SELECT
000 = ROW 1
110 = ROW 7
D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀
XXX
DOT DATA
UDC RAM
C
C
DATA FORMAT
O
O
L
L
1
5
0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
Figure 3. Logic levels to access a UDC character.
RST CE WR RD
0 0 UNDEFINED
1
0
0
1
1 WRITE TO DISPLAY
0 READ FROM DISPLAY
1 1 UNDEFINED
CONTROL SIGNALS
FL A₄ A₃ A₂ A₁ A₀
0X X
CHARACTER
ADDRESS
FLASH RAM ADDRESS
000 = LEFT MOST
111 = RIGHT MOST
D₇ D₆ D₅ D₄ D₃ D₂ D₁ D_{0 REMOVE FLASH AT}
X
X
X
X
X
X
X
0 _{SPECIFIED DIGIT LOCATION}
1 _{STORE FLASH AT}
FLASH RAM DATA FORMAT
SPECIFIED DIGIT LOCATION
0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
Figure 5. Logic levels to access the Flash RAM.
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