HFBR-5961ALZ Datasheet, PDF (4/13 Pages) AVAGO TECHNOLOGIES LIMITED – Multimode Small Form Factor (SFF) Transceivers for ATM, FDDI, Fast Ethernet and SONET OC-3/SDH STM-1 with LC connector

Recommended Handing Precautions
Avago recommends that normal status precautions be
taken in the handling and assembly of these transceiv-
ers to prevent damage which may be induced by elec-
trostatic discharge (ESD). The HFBR-5961xxZ series of
transceivers meet MIL-STD-883C Method 3015.4 Class 2
products.
Care should be used to avoid shorting the receiver data
or signal detect outputs directly to ground without
proper current limiting impedance.
Solder and Wash Process Compatibility
The transceivers are delivered with protective process
plugs inserted into the LC receptacle.
This process plug protects the optical subassemblies
during wave solder and aqueous wash processing and
acts as a dust cover during shipping.
These transceivers are compatible with either industry
standard wave or hand solder processes.
Shipping Container
The transceiver is packaged in a shipping container
designed to protect it from mechanical and ESD
damage during shipment of storage.
Board Layout - Decoupling Circuit, Ground Planes and Termi-
nation Circuits
It is important to take care in the layout of your circuit
board to achieve optimum performance from these
transceivers. Figure 3 provides a good example of a
schematic for a power supply decoupling circuit that
works will with these parts, It is further recommend-
ed that a contiguous ground plane be provided in the
circuit board directly under the transceiver to provide
a low inductance ground for signal return current.
This recommendation is in keeping with good high
frequency board layout practices.Figures 3 and 4 show
two recommended termination schemes.
TERMINATE AT
TRANSCEIVER INPUTS
Z = 50 Ω
100 Ω
Z = 50 Ω
10 9 8 7 6
TX
RX
12345
1 µH
C2
1 µH
C1
VCC(+3.3 V)
C3
10 µF
Z = 50 Ω
Z = 50 Ω
130 Ω 130 Ω
Z = 50 Ω
Notes:
C1 = C2 = C3 = 10 nF or 100 nF
* Loading of R1 is optional.
Figure 3. Recommended Decoupling and Termination Circuits

PHY DEVICE
VCC(+3.3 V)
TD-
TD+
130 Ω 130 Ω
LVPECL
VCC(+3.3 V)
RD+
100 Ω
RD-
VCC(+3.3 V)
130 Ω
SD
82 Ω
LVPECL
LVTTL
TERMINATE AT
DEVICE INPUTS