ADNS-7700 Datasheet, PDF (19/60 Pages) AVAGO TECHNOLOGIES LIMITED – One chip USB LaserStream Mouse Sensors Single 5.0 volts power supply

OTP Lock Operation
OTP lock operation MUST be performed once OTP write to
OTPLOCK2 register for the sensor to function. DO not reset
or power up the chip right after OTP write to OTPLOCK2
register, otherwise the chip will be malfunction. The OTP
lock operation flow chart is shown in Figure 18.
1. After OTP write to OTPLOCK2 register, set OTP enable
bit in OTP_CONFIG register, 0x4C: OTP_EN = 1.
2. Set OTP lock bit in OTP_CTRL register, 0x4F to enable
OTP lock command: LOCK_L2 = 1.
3. Read the OTP lock bit status in OTP_CTRL register, 0x4F. If
LOCK_L2 = 1, repeat reading the bit status until it is clear.
4. Read the lock status and CRC bits in OTP_CTRLSTAT
register, 0x50.
a. If both L2_LOCK_OK and L2_CRC_OK = 1, OTP lock
operation is completed.
b. If either L2_LOCK_OK or L2_CRC_OK = 0, repeat Step
2 until both bits are set.
5. If Step 4b is repeated up to 10 times, OTP lock operation
is failed and the chip is confirmed as defective unit.
OTP Write 0xFF to
OTPLOCK2 register,
0xFA
Write OTP enable bit
0x4C: OTP_CONFIG [0] = 1
Repeat = 1
Write OTP lock bit
Read OTP lock bit
No
bit = 0?
0x4F: OTP_CTRL [2] = 1
0x4F: OTP_CTRL [2]
Repeat = repeat + 1
No
Yes
Read lock status bit
Read CRC status bit
0x50: OTP_CTRLSTAT [2]
0x50: OTP_CTRLSTAT [3]
Repeat = 10?
No
lock & crc = 1?
Yes
OTP lock fail
Yes
OTP locked
Bad chip
Done
Figure 18. OTP Byte Lock Flow Chart
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