ADNS-7700 Datasheet, PDF (17/60 Pages) AVAGO TECHNOLOGIES LIMITED – One chip USB LaserStream Mouse Sensors Single 5.0 volts power supply

One-Time-Programmable (OTP) Memory
The on chip OTP memory allows device configuration flex-
ibility to override the default setting of ADNS-7700 sensors
without any external software driver. Once the OTP op-
eration is enabled, all OTP registers must be programmed
accordingly as the default values of un-program OTP reg-
isters are always zero when L2_USE_OTP register setting is
not zero value. Tips: OTP write to the OTP register can be
skipped if the setting is zero value (0x00) in order to save
the OTP programming time.
OTP address space is from 0x80 to 0xFE. OTP can be pro-
grammed via USB interface using Set Vendor Test and Get
Vendor Test commands.
OTP Byte Write Operation
OTP write operation flow chart is shown in Figure 16.
1. Set OTP enable bit in OTP_CONFIG register, 0x4C:
OTP_EN = 1.
2. Write the OTP register address byte to OTP_ADDR
register, 0x4D.
3. Write the OTP data byte to OTP_DATA register, 0x4E.
4. Set write enable bit in OTP_CTRL register, 0x4F to
enable write command to OTP: WR = 1.
5. Read the write enable bit status in OTP_CTRL register,
0x4F. If WR = 1, repeat reading the bit status until it is
clear.
6. Read the write status bit in OTP_CTRLSTAT register,
0x50.
a. If WR_OK = 1, OTP write operation is completed.
Repeat Step 2 for more OTP byte write operations.
b. If WR_OK = 0, repeat Step 4.
7. If Step 6b is repeated up to 10 times, OTP write operation
is failed and the chip is confirmed as defective unit.
Start
Write OTP enable bit
0x4C: OTP_CONFIG [0] = 1
0x4F: OTP_CTRL [0] = 1
0x4F: OTP_CTRL [0]
0x50: OTP_CTRLSTAT [0]
Repeat = 1
Write OTP addr byte
Write OTP data byte
Write OTP program bit
Read OTP program bit
No
bit = 0?
Yes
Yes
Read OTP status bit
0x4D: OTP_ADDR [7:0]
0x4E: OTP_DATA [7:0]
Repeat = repeat + 1
No
bit = 1?
No Repeat = 10?
Yes
OTP write pass
Yes
OTP write fail
More bytes?
Bad chip
No
Done
Figure 16. OTP Byte Write Flow Chart
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