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HCPL-7800-500E Datasheet, PDF (14/18 Pages) AVAGO TECHNOLOGIES LIMITED – 15 kV/μs Common-Mode Rejection at VCM = 1000 V
As shown in Figure 18, 0.1 µF bypass capacitors (C1, C2)
should be located as close as possible to the pins of the
HCPL-7800(A). The bypass capacitors are required because
of the high-speed digital nature of the signals inside the
HCPL-7800(A). A 0.01 µF bypass capacitor (C2) is also rec-
ommended at the input due to the switched-capacitor
nature of the input circuit. The input bypass capacitor
also forms part of the anti-aliasing filter, which is recom-
mended to prevent high-frequency noise from aliasing
down to lower frequencies and interfering with the input
signal. The input filter also performs an important reliabil-
ity function—it reduces transient spikes from ESD events
flowing through the current sensing resistor.
PC Board Layout
The design of the printed circuit board (PCB) should follow
good layout practices, such as keeping bypass capacitors
close to the supply pins, keeping output signals away
from input signals, the use of ground and power planes,
etc. In addition, the layout of the PCB can also affect the
isolation transient immunity (CMTI) of the HCPL-7800(A),
due primarily to stray capacitive coupling between the
input and the output circuits. To obtain optimal CMTI
performance, the layout of the PC board should minimize
any stray coupling by maintaining the maximum possible
distance between the input and output sides of the circuit
and ensuring that any ground or power plane on the PC
board does not pass directly below or extend much wider
than the body of the HCPL-7800(A).
POSITIVE
FLOATING
SUPPLY
HV+
C5
150 pF
MOTOR
***
+-
RSENSE
GATE DRIVE
CIRCUIT
***
U1
78L05
IN OUT
C1
C2
1
0.1
0.1
µF
µF
R5
2
68
C3
0.01
µF
3
4
***
U2
HCPL-7800
+5 V
8
C4
0.1 µF
7
R1
2.00 K
6
R2
2.00 K
5
C6
150 pF
R3
10.0 K
+15 V
C8
0.1 µF
-
U3
+ MC34081
C7
R4
10.0 K
0.1 µF
-15 V
VOUT
HV-
Figure 18: Recommended Application Circuit.
R5
C2 C4
C3
TO VDD1
TO RSENSE+
TO RSENSE-
TO VDD2
VOUT+
VOUT-
Figure 19. Example Printed Circuit Board Layout.
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