HCPL-7800-500E Datasheet, PDF (10/18 Pages) AVAGO TECHNOLOGIES LIMITED – 15 kV/μs Common-Mode Rejection at VCM = 1000 V

V_DD1
0.1 µF
V_DD2
1
8
0.1 µF
2
7
10 K
HCPL-7800
3
6
10 K
4
5
0.47
µF
Figure 1. Input Offset Voltage Test Circuit.
+15 V
0.1 µF
+
- _AD624CD
GAIN = 100
0.47
0.1 µF
µF
-15 V
VOUT
0.8
0.7
0.6
0.5
0.4
0.3
0.2
-55 -25 5 35 65 95 125
TA - TEMPERATURE - ˚C
Figure 2. Input Offset Voltage vs. Temperature.
0.39
vs. VDD1
0.38
vs. VDD2
0.37
0.36
0.35
0.34
0.33
4.5
4.75
5.0
5.25
5.5
VDD - SUPPLY VOLTAGE - V
Figure 3. Input Offset vs. Supply.
8.035
8.03
8.025
8.02
8.015
8.01
-55 -35 -15 5 25 45 65 85 105 125
TA - TEMPERATURE - ¡C
Figure 4. Gain vs. Temperature.
V_DD1
404
V_IN
1
0.1 µF
2
13.2
3
0.01 µF
4
HCPL-7800
V_DD2
8
0.1 µF
7
10 K
6
10 K
5
0.47
µF
Figure 5. Gain and Nonlinearity Test Circuit.
+15 V
0.1 µF
+15 V
0.1 µF
+
- _AD624CD
GAIN = 4
0.47
0.1 µF
µF
-15 V
10 K
0.47
µF
+
- _AD624CD
GAIN = 10
0.1 µF
VOUT
-15 V
10