HCPL-0708-560E Datasheet, PDF (10/12 Pages) AVAGO TECHNOLOGIES LIMITED – High Speed CMOS Optocoupler

Application Information
Bypassing and PC Board Layout
The HCPL-0708 optocoupler is extremely easy to use. No
external interface circuitry is required because the HCPL-
0708 uses high-speed CMOS IC technology allowing
CMOS logic to be connected directly to the inputs and
outputs.
As shown in Figure 6, the only external component re-
quired for proper operation is the bypass capacitor. Ca-
pacitor values should be between 0.01 µF and 0.1 µF. For
each capacitor, the total lead length between both ends
of the capacitor and the power-supply pins should not
exceed 20 mm. Figure 7 illustrates the recommended
printed circuit board layout for the HPCL-0708.
1
I_F
2
3
4
8
V_DD
C
7 NC
6
V_O
5
GND
C1, C2 = 0.01 µF TO 0.1 µF
Figure 6. Recommended printed circuit board layout.
V_DD
I_F
C2
V_O
Figure 7. Recommended printed circuit board layout.
GND
C1, C2 = 0.01 µF TO 0.1 µF
Propagation Delay, Pulse-Width Distortion and Propagation
Delay Skew
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a sys-
tem. The propaga­tion delay from low to high (t_PLH) is the
amount of time required for an input signal to propagate
to the output, causing the output to change from low
to high. Similarly, the propagation delay from high to
low (t_PHL) is the amount of time required for the input
signal to propagate to the output, causing the output to
change from high to low. See Figure 8.
INPUT
I_F
OUTPUT
V_O
10%
t_PLH
90%
Figure 8.
t_PHL
50%
90%
10%
12 mA
0 mA
V_OH
2.5 V CMOS
V_OL
10