SAM3S_14 Datasheet, PDF (952/1087 Pages) ATMEL Corporation – AT91SAM ARM-based Flash MCU

Figure 40-5. GOVRE and OVREx Flag Behavior
Trigger event
CH0
(ADC_CHSR)
CH1
(ADC_CHSR)
ADC_LCDR
ADC_CDR0
ADC_CDR1
EOC0
(ADC_SR)
EOC1
(ADC_SR)
Undefined Data
Data A
Undefined Data
Undefined Data
Conversion A
Data B
Data A
Data B
Conversion C
Conversion B
Data C
Data C
Read ADC_CDR0
Read ADC_CDR1
GOVRE
(ADC_SR)
DRDY
(ADC_SR)
OVRE0
(ADC_OVER)
OVRE1
(ADC_OVER)
Read ADC_SR
Read ADC_OVER
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during
a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable.
40.6.5 Conversion Triggers
Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is
provided by writing the Control Register (ADC_CR) with the START bit at 1.
The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, PWM Event line, or the exter-
nal trigger input of the A(ADTRG). The hardware trigger is selected with the TRGSEL field in the Mode Register
(ADC_MR). The selected hardware trigger is enabled with the TRGEN bit in the Mode Register (ADC_MR).
The minimum time between 2 consecutive trigger events must be strictly greater than the duration time of the lon-
gest conversion sequence according to configuration of registers ADC_MR, ADC_CHSR, ADC_SEQR1,
ADC_SEQR2.
SAM3S [DATASHEET]
6500E–ATARM–11-Feb-13
952