SAM3S_14 Datasheet, PDF (154/1087 Pages) ATMEL Corporation – AT91SAM ARM-based Flash MCU

11.19.7.4 IPR2
31
30
29
28
27
26
25
24
IP[11]
23
22
21
20
19
18
17
16
IP[10]
15
14
13
12
11
10
9
8
IP[9]
7
6
5
4
3
2
1
0
IP[8]
11.19.7.5 IPR1
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
IP[6]
15
14
13
12
11
10
9
8
IP[5]
7
6
5
4
3
2
1
0
IP[4]
11.19.7.6 IPR0
31
30
29
28
27
26
25
24
IP[3]
23
22
21
20
19
18
17
16
IP[2]
15
14
13
12
11
10
9
8
IP[1]
7
6
5
4
3
2
1
0
IP[0]
• Priority, byte offset 3
• Priority, byte offset 2
• Priority, byte offset 1
• Priority, byte offset 0
Each priority field holds a priority value, 0-15. The lower the value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
See “The CMSIS mapping of the Cortex-M3 NVIC registers” on page 146 for more information about the IP[0] to IP[34]
interrupt priority array, that provides the software view of the interrupt priorities.
Find the IPR number and byte offset for interrupt N as follows:
SAM3S [DATASHEET]
6500E–ATARM–11-Feb-13
154