SAM3S_14 Datasheet, PDF (696/1087 Pages) ATMEL Corporation – AT91SAM ARM-based Flash MCU

• SYNC: Synchronous Mode Select
0: USART operates in Asynchronous Mode.
1: USART operates in Synchronous Mode.
• CPHA: SPI Clock Phase
– Applicable if USART operates in SPI Mode (USART_MODE = 0xE or 0xF):
CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
• PAR: Parity Type
Value
0
1
2
3
4
6
Name
EVEN
ODD
SPACE
MARK
NO
MULTIDROP
Description
Even parity
Odd parity
Parity forced to 0 (Space)
Parity forced to 1 (Mark)
No parity
Multidrop mode
• NBSTOP: Number of Stop Bits
Value
0
1
2
Name
1_BIT
1_5_BIT
2_BIT
• CHMODE: Channel Mode
Description
1 stop bit
1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
2 stop bits
Value
0
1
2
3
Name
NORMAL
AUTOMATIC
LOCAL_LOOPBACK
REMOTE_LOOPBACK
Description
Normal Mode
Automatic Echo. Receiver input is connected to the TXD pin.
Local Loopback. Transmitter output is connected to the Receiver Input.
Remote Loopback. RXD pin is internally connected to the TXD pin.
• MSBF: Bit Order
0: Least Significant Bit is sent/received first.
1: Most Significant Bit is sent/received first.
• CPOL: SPI Clock Polarity
– Applicable if USART operates in SPI Mode (Slave or Master, USART_MODE = 0xE or 0xF):
CPOL = 0: The inactive state value of SPCK is logic level zero.
CPOL = 1: The inactive state value of SPCK is logic level one.
SAM3S [DATASHEET]
6500E–ATARM–11-Feb-13
696