AT91SAM9G45_1 Datasheet, PDF (930/1159 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

AT91SAM9G45
The Linked List multi-buffer transfer is initiated by programming DMAC_DSCRx with DSCRx(0)
(LLI(0) base address) and DMAC_CTRLBx register with both SRC_DSCR and DST_DSCR set
to 0. Other fields and registers are ignored and overwritten when the descriptor is retrieved from
memory.
The last transfer descriptor must be written to memory with its next descriptor address set to 0.
Figure 41-5. Multi Buffer Transfer Using Linked List
LLI(0)
System Memory
LLI(1)
DSCRx(1)_{= DSCRx(0) + 0x10}
CTRLBx_{= DSCRx(0) + 0xC}
CTRLAx_{= DSCRx(0) + 0x8}
DSCRx(2)_{= DSCRx(1) + 0x10}
CTRLBx_{= DSCRx(1) + 0xC}
CTRLBx_{= DSCRx(1) + 0x8}
DADDRx_{= DSCRx(0) + 0x4}
DADDRx_{= DSCRx(1) + 0x4}
DSCRx(0)
SADDRx_{= DSCRx(0) + 0x0}
DSCRx(1)
SADDRx_{= DSCRx(1) + 0x0}
DSCRx(2)
(points to 0 if
LLI(1) is the last
transfer descriptor
6438D–ATARM–13-Oct-09
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