AT91SAM9G45_1 Datasheet, PDF (240/1159 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

Figure 22-8. Write Command Followed By a Read Command without Burst Write Interrupt, Low-power DDR1-SDRAM
Device
SDCLK
A[12:0]
COMMAND
NOP
col a
WRITE
NOP
col a
READ BST
NOP
BA[1:0] 0
DQS[1:0]
DM[1:0] 3
D[15:0]
0
3
Da Db Dc Dd De Df Dg Dh
Twrd = BL/2 +2 = 8/2 +2 = 6
Da Db
Twr = 1
In the case of a single write access, write operation should be interrupted by a read access but
DM must be input 1 cycle prior to the read command to avoid writing invalid data. See Figure 22-
9 on page 238.
Figure 22-9. Single Write Access Followed By A Read Access Low-power DDR1-SDRAM Devices
SDCLK
A[12:0]
Row a
col a
COMMAND ^NOP
PRCHG NOP ACT NOP WRITE
NOP
READ BST
NOP
BA[1:0] ⁰
DQS[1:0]
DM[1:0] ³
D[15:0]
0
3
Da
Db
Da Db
Data masked
238 AT91SAM9G45
6438D–ATARM–13-Oct-09