AT91SAM9G45_1 Datasheet, PDF (1086/1159 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

AT91SAM9G45
45.12.12 LCD Timing Configuration Register 1
Name: LCDTIM1
Address:0x00500808
Access: Read-write
Reset value: 0x0000000
31
30
29
28
27
26
25
24
1
–
–
–
VHDLY
23
22
21
20
19
18
17
16
–
–
VPW
15
14
13
12
11
10
9
8
VBP
7
6
5
4
3
2
1
0
VFP
• VFP: Vertical Front Porch
In TFT mode, these bits equal the number of idle lines at the end of the frame.
In STN mode, these bits should be set to 0.
• VBP: Vertical Back Porch
In TFT mode, these bits equal the number of idle lines at the beginning of the frame.
In STN mode, these bits should be set to 0.
• VPW: Vertical Synchronization pulse width
In TFT mode, these bits equal the vertical synchronization pulse width, given in number of lines. LCDVSYNC width is equal
to (VPW+1) lines.
In STN mode, these bits should be set to 0.
• VHDLY: Vertical to horizontal delay
In TFT mode, this is the delay between LCDVSYNC rising or falling edge and LCDHSYNC rising edge. Delay is
(VHDLY+1) LCDDOTCK cycles. Bit 31 must be written to 1.
In STN mode, these bits should be set to 0.
6438D–ATARM–13-Oct-09
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