AT91SAM9G45_1 Datasheet, PDF (258/1159 Pages) ATMEL Corporation – AT91 ARM Thumb-based Microcontrollers

22.6
Programmable IO Delays
The external bus interface consists of a data bus, an address bus and control signals. The simul-
taneous switching outputs on these busses may lead to a peak of current in the internal and
external power supply lines.
In order to reduce the peak of current in such cases, additional propagation delays can be
adjusted independently for pad buffers by means of configuration registers,
DDRSDRC_DELAY1-8.
The additional programmable delays for each IO range from 0 to 4 ns (Worst Case PVT). The
delay can differ between IOs supporting this feature. Delay can be modified per programming for
each IO. The minimal additional delay that can be programmed on a PAD supporting this feature
is 1/16 of the maximum programmable delay.
When programming 0x0 in fields “Delay1 to Delay8”, no delay is added (reset value) and the
propagation delay of the pad buffers is the inherent delay of the pad buffer. When programming
0xF in field “Delay1” the propagation delay of the corresponding pad is maximal.
DDRSDRC_DELAY1, DDRSDRC_DELAY2 allow to configure delay on D[15:0],
DDRSDRC_DELAY1[3:0] corresponds to D[0] and DDRSDRC_DELAY2[3:0] corresponds to
D[8].
DDRSDRC_DELAY3, DDRSDRC_DELAY4 allow to configure delay on A13:0],
DDRSDRC_DELAY3[3:0] corresponds to A[0] and DDRSDRC_DELAY4[3:0] corresponds to
A[8].
Figure 22-26. Programmable IO Delays
SMC
D_in[0]
D_out[0]
DELAY1
D_in[1]
D_out[1]
DELAY2
Programmable Delay Line
D[0]
Programmable Delay Line
D[1]
D_in[n]
D_out[n]
DELAYx
Programmable Delay Line
D[n]
A[m]
DELAYy
Programmable Delay Line
A[m]
22.7 DDR-SDRAM Controller (DDRSDRC) User Interface
The User Interface is connected to the APB bus.
256 AT91SAM9G45
6438D–ATARM–13-Oct-09