AT91SAM9G25-CU Datasheet, PDF (929/1102 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

43.8.1 Write Protection Registers
To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Protect Status Register
(US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the SSC Write Protect Mode Register (SSC_WPMR) with the appropriate access key,
WPKEY.
The protected registers are:
z “SSC Clock Mode Register” on page 932
z “SSC Receive Clock Mode Register” on page 933
z “SSC Receive Frame Mode Register” on page 935
z “SSC Transmit Clock Mode Register” on page 937
z “SSC Transmit Frame Mode Register” on page 939
z “SSC Receive Compare 0 Register” on page 943
z “SSC Receive Compare 1 Register” on page 943
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
929