AT91SAM9G25-CU Datasheet, PDF (464/1102 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

5. Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx registers
for channel x. For example, in the register, you can program the following:
z i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control
device by programming the FC of the DMAC_CTRLBx register.
z ii. Set up the transfer characteristics, such as:
z Transfer width for the source in the SRC_WIDTH field.
z Transfer width for the destination in the DST_WIDTH field.
z Source AHB Master interface layer in the SIF field where source resides.
z Destination AHB Master Interface layer in the DIF field where destination resides.
z Incrementing/decrementing or fixed address for source in SRC_INC field.
z Incrementing/decrementing or fixed address for destination in DST_INC field.
6. Write the channel configuration information into the DMAC_CFGx register for channel x.
z i. Designate the handshaking interface type (hardware or software) for the source and destination
peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL
bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination
requests. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests.
z ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign a
handshaking interface to the source and destination peripheral. This requires programming the SRC_PER
and DST_PER bits, respectively.
7. If source Picture-in-Picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the
DMAC_SPIPx register for channel x.
8. If destination Picture-in-Picture mode is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the
DMAC_DPIPx register for channel x.
4. After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the
DMAC_CHER.ENAx bit, where x is the channel number. Make sure that bit 0 of DMAC_EN.ENABLE register is
enabled.
5. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-
memory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the
buffer and carries out the buffer transfer.
6. Once the transfer completes, the hardware sets the interrupts and disables the channel. At this time, you can
either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or poll
for the Channel Handler Status Register (DMAC_CHSR.ENAx) bit until it is cleared by hardware, to detect when
the transfer is complete.
Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4)
1. Read the Channel Handler Status register to choose a free (disabled) channel.
2. Set up the chain of Linked List Items (otherwise known as buffer descriptors) in memory. Write the control informa-
tion in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers location of the buffer descriptor for each LLI in
memory (see Figure 31-6 on page 466) for channel x. For example, in the register, you can program the following:
1. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control
device by programming the FC of the DMAC_CTRLBx register.
2. Set up the transfer characteristics, such as:
z i. Transfer width for the source in the SRC_WIDTH field.
z ii. Transfer width for the destination in the DST_WIDTH field.
z iii. Source AHB master interface layer in the SIF field where source resides.
z iv. Destination AHB master interface layer in the DIF field where destination resides.
z v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
z vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
464