AT91SAM9G25-CU Datasheet, PDF (666/1102 Pages) ATMEL Corporation – AT91SAM ARM-based Embbedded MPU

Value
8
9
10
11
12
13
14
15
Name
16_BIT
–
–
–
–
–
–
–
Description
16 bits for transfer
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud
rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:
SPCK Baudrate = -^M------^C----^K---
SCBR
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
Note:
If one of the SCBR fields inSPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as well, if they
are required to process transfers. If they are not used to transfer data, they can be set at any value.
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
Delay Before SPCK = ^D-----^L----^Y----^B----^S-
MCK
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The
delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the char-
acter transfers.
Otherwise, the following equation determines the delay:
Delay Between Consecutive Transfers = ³----²-----^×-----^D-----^L----^Y----^B----^C----^T--
MCK
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
666